Dual-Cool Power Module With Stress Buffer for CTE Mismatch

The patent introduces a stress buffer layer as an intermediary component between the heatsink and the semiconductor die. This stress buffer layer has a CTE that is intermediate between the heatsink and the semiconductor die, acting as a mediator that gradually transitions the thermal expansion stress rather than creating a abrupt mismatch. This resolves the CTE mismatch problem while maintaining the functional integration of multiple materials in the power module package.

The patent transitions from conventional planar heat sinking to a three-dimensional pin-fin heatsink structure. The pin-fins extend vertically from the heatsink base, creating additional surface area in the vertical dimension. This dimensional change dramatically increases the thermal dissipation capacity while maintaining compatibility with conventional packaging assembly processes.

The patent changes the CTE parameter of the interface between heatsink and semiconductor die by inserting a stress buffer layer with intermediate CTE properties. This parameter modification allows the use of materials with different CTE values (maintaining material selection flexibility) while the intermediate CTE of the stress buffer layer prevents the formation of high-stress interfaces that would cause electrical failures.

The patent employs a pin-fin heatsink structure that can be considered a porous-like geometry with numerous vertical fins creating a high-surface-area network. This porous-like structure achieves enhanced thermal dissipation through its internal geometry rather than by increasing the overall package size, thereby improving thermal reliability without proportionally increasing device complexity.