Dual-Side Cooled Power Transistor Package With DBC Substrates
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Solution Overview
Problem
Existing packaged electronic devices, particularly those with large dimensions and high power switching currents, face inefficiencies in heat dissipation, especially when they have different circuit topologies, leading to unsuitable overall dimensions and inadequate cooling.
Innovation Solution
A packaged electronic device with a Double Cooling (DC) configuration using DBC substrates and a thermally conductive body, allowing heat dissipation on both sides and enabling various circuit topologies, including inverters, by interposing a DBC substrate between power components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional single-side cooling packages are used for high power MOSFET transistors, then the package structure is simple, but the thermal dissipation efficiency is insufficient and package dimensions become unsuitable
Solution Approach 1:
The cooling function is segmented into two independent cooling paths, one for each substrate, allowing each side to dissipate heat independently. This segmentation enables the package to handle high power applications more effectively by distributing thermal load across multiple pathways rather than relying on a single cooling interface.
Solution Approach 2:
The invention transitions from single-side cooling to dual-side cooling, utilizing both the upper and lower surfaces of the package for heat dissipation. This dimensional change in the cooling approach doubles the effective heat dissipation area and enables more efficient thermal management for high power devices.
2Temperature
If conventional packages are used for large dimension power components, then the components can be accommodated, but the overall package dimensions become unsuitable and dissipation is limited
Solution Approach 1:
By utilizing both the top and bottom surfaces of the package for cooling, the invention effectively doubles the heat dissipation area without proportionally increasing the package volume. This allows large power components to be accommodated with improved thermal performance while maintaining compact overall dimensions.
Solution Approach 2:
The invention combines multiple functional elements into an integrated dual-cooling structure where substrates, heat sinks, and thermal pathways are merged into a cohesive package design. This integration achieves efficient heat dissipation while minimizing the overall package footprint.
3Power
If high power components with high switching currents are used, then the power handling capability increases, but the thermal management becomes more challenging
Solution Approach 1:
The thermal management system is segmented into independent cooling paths for each substrate, allowing heat from high power components to be distributed and dissipated through multiple pathways. This segmentation prevents thermal bottlenecks and enables effective heat management even as power handling capability increases.
Solution Approach 2:
Thermally conductive substrates act as intermediaries between the high power components and the cooling structures, efficiently transferring heat away from the power devices. These substrates serve as thermal mediators that enable high power handling while maintaining manageable thermal conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DC configuration provides efficient thermal dissipation, reduces device thickness, and allows for compact designs suitable for high-voltage applications with improved reliability and reduced inductive parasitic effects.
Implementation Method 1
at least two power components are attached to respective electrically insulating and thermally conductive elements, for example DBC (Direct Bonded Copper) substrates and a thermally conductive body (for example a third DBC) is interposed between the power components
Data Source
Figure 1~3I
Figure 4~7
Figure 8A~9B
AI summary
Electronic device (50) comprising at least a first and a second branch (21A, 21B, 21C), each branch including a first and a second transistor (23, 24) arranged in series to each other and formed in respective dice (51) of semiconductor material. The dice (51) are sandwiched between a first substrate element (55) and a second substrate element (56). The first and the second substrate elements (55, 56) are formed each by a multilayer including a first conductive layer (57), a second conductive layer (58) and an insulating layer (59) extending between the first and the second conductive layers. The first conductive layers (57) of the first and the second substrate elements (55, 56) face towards the outside of the electronic device and define a first and a second main face of the electronic device. The second conductive layer (58) of the first and the second substrate elements (55, 56) is shaped so as to form contact regions (52A-52F, 33A-33D) facing and in selective electrical contact with the plurality of dice (51).