Dual-Core Radix Sort Accelerator Parallel Processing
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Solution Overview
Problem
Existing sorting algorithms, such as radix sort, face challenges in high-performance hardware implementation due to read-write dependency and load-balancing issues, especially in in-place radix sort for skewed data distributions and large memory footprints.
Innovation Solution
A dual-core radix sort accelerator with a pre-fetching engine and buffer memory architecture that allows parallel processing of data elements from both ends of an array, using a dual-core processor system to efficiently manage memory and reduce latency, and a custom pre-fetching engine to handle memory access efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If in-place radix sort is used to reduce memory overhead, then memory efficiency is improved, but read-write dependency and load-balancing difficulties worsen
Solution Approach 1:
The patent divides the sorting array into multiple segments or buckets that can be processed independently. By segmenting the data, the system reduces read-write dependencies within each segment while maintaining overall sorting efficiency. This allows parallel processing of different segments without conflicting memory access patterns.
Solution Approach 2:
The patent introduces intermediary buffer structures and pointer mechanisms that mediate between the input array and the sorting buckets. These intermediaries decouple the read-write operations, allowing the algorithm to progress without direct conflicts between reading and writing the same memory locations.
2Device complexity
If traditional single-processor radix sort is used, then implementation simplicity is improved, but processing throughput worsens
Solution Approach 1:
The patent segments the sorting work across multiple processors, with each processor handling specific ranges or buckets of data. This division of labor increases throughput while keeping each processor's implementation relatively simple and modular.
Solution Approach 2:
The patent transitions from a single-processor sequential approach to a multi-processor parallel architecture, adding the dimension of parallelism. This allows simultaneous processing of multiple data elements, significantly improving throughput while maintaining implementation simplicity through standardized processor designs.
3Loss of time
If radix sort is applied to skewed data distributions, then linear time complexity is maintained, but load-balancing across buckets worsens
Solution Approach 1:
The patent implements dynamic load-balancing mechanisms that adapt to skewed data distributions. The system can dynamically adjust bucket assignments, redistribute elements, or rebalance workloads across processors based on the actual data distribution, maintaining linear time complexity even when input data is highly skewed.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor bucket sizes and distribution patterns during the sorting process. Based on this feedback, the system can adjust its sorting strategy, redistribute elements, or optimize processor assignments to handle skewed distributions effectively while maintaining overall linear time complexity.
Data Source
AI summary
An information processing system, computer readable storage medium, and method for accelerated radix sort processing of data elements in an array in memory. The information processing system stores an array of data elements in a buffer memory in an application specific integrated circuit radix sort accelerator. The array has a head end and a tail end. The system radix sort processing, with a head processor, data elements starting at the head end of the array and progressively advancing radix sort processing data elements toward the tail end of the array. The system radix sort processing, with a tail processor, data elements starting at the tail end of the array and progressively advancing radix sort processing data elements toward the head end of the array, the tail processor radix sort processing data elements in the array contemporaneously with the head processor radix sort processing data elements in the array.