Dual-Core Reset Sequencing Without RTC Data Loss
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Solution Overview
Problem
Existing dual-core electronic devices face instability when processor cores malfunction, requiring a reset operation that often results in data loss in real-time clock registers due to complete power-off, affecting time accuracy.
Innovation Solution
A method for resetting dual-core processors without complete power-off by using specific pin connections and control signals between processor cores and a power management unit to determine the origin of the reset signal, allowing controlled reset sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complete power-off is performed to reset dual-core processors, then reset operation can be implemented, but real-time clock register data is lost affecting time accuracy
Solution Approach 1:
The reset operation is segmented into two independent parts: power management unit reset and processor core reset. The power management unit maintains power supply and preserves real-time clock data, while only the processor core undergoes reset. This segmentation allows selective resetting without complete power-off, resolving the contradiction between reset capability and data preservation.
Solution Approach 2:
The power management unit acts as an intermediary between the reset signal and the processor core. It receives reset signals, determines their origin (internal or external), and selectively applies them to the processor core while maintaining power supply to preserve real-time clock data. This intermediary function enables controlled resetting without complete power cycling.
2Device complexity
If reset signal origin is not tracked, then simple reset implementation is achieved, but inability to determine whether reset should trigger dual-core reset or single-core reset
Solution Approach 1:
The system implements feedback by tracking the origin of reset signals through status pins. When an external reset signal is detected, the power management unit sets a status pin to indicate the reset source. This feedback mechanism enables the system to differentiate between internal and external reset origins, determining whether to perform single-core or dual-core reset accordingly, without significantly increasing complexity.
Data Source
AI summary
An electronic device includes a first processor core, a second processor core, a power management unit. A first output pin of the first processor core is connected to a first input pin of the second processor core, a first reset pin of the first processor core is connected to a first control pin of the second processor core, a second reset pin of the second processor core is separately connected to a second control pin of the first processor core and a third control pin of the power management unit. The second processor core is configured to: enter a reset state after the second reset pin of the second processor core receives a reset signal; if the first input pin is in the first state, send a reset signal to the first reset pin by using the first control pin, for the first processor core to enter a reset state.