Dual-Core Processor with Dynamic RISC CISC Switching
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Solution Overview
Problem
Designing portable electronic devices poses challenges in minimizing power consumption and thermal output while incorporating increasing functionality, as existing solutions often compromise between using RISC and CISC processors, which affects battery life and heat generation.
Innovation Solution
A processor integrated circuit (IC) combining a RISC core, a CISC core, video, and audio accelerators, allowing the RISC core to be active in power-saving modes and both cores to be active in functional modes, with the CISC core providing primary control for high-level operating systems and graphical interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a CISC processor is used to provide high-level operating system functionality, then device functionality is improved, but power consumption and thermal output increase
Solution Approach 1:
The processor is divided into two separate cores: a RISC core for basic operations and a CISC core for advanced functionality. This segmentation allows the system to use only the necessary core for each task, reducing overall power consumption while maintaining full functionality when needed.
Solution Approach 2:
The system dynamically switches between RISC-only mode and dual-core mode based on operational requirements. The mode selection circuitry automatically determines whether to activate the CISC core based on the current task, enabling the processor to adapt its power consumption to actual functional needs.
2Adaptability or versatility
If both RISC and CISC cores are active to provide full functionality, then device adaptability is improved, but power consumption increases
Solution Approach 1:
The processor implements dynamic core activation where the CISC core is activated only when advanced functionality is required. The mode selection circuitry monitors system needs and dynamically switches between RISC-only operation and dual-core operation, ensuring full functionality is available when needed while minimizing power consumption during basic operations.
Solution Approach 2:
Different operational modes provide different quality levels of processing power. Basic operations use the efficient RISC core, while complex operations engage the more powerful CISC core. This local quality approach ensures that full functionality is available when needed without paying the power consumption cost continuously.
3Use of energy by moving object
If a RISC processor is used to minimize power consumption, then energy efficiency is improved, but device functionality is limited
Solution Approach 1:
The processing system is segmented into a RISC core for efficient basic operations and a CISC core for advanced functionality. This segmentation allows the system to maintain low power consumption for everyday tasks while providing full functionality when needed by activating the CISC core.
Solution Approach 2:
The dual-core processor provides universal functionality by combining both RISC and CISC capabilities in a single device. The system can handle both basic and advanced operations, making it universally applicable to a wide range of tasks while maintaining energy efficiency through selective core activation.
4Adaptability or versatility
If dual-core processor is used to provide full functionality, then device adaptability is improved, but thermal output increases
Solution Approach 1:
The processor implements dynamic thermal management by activating the CISC core only when advanced functionality is required. This dynamic approach reduces continuous heat generation from the CISC core while maintaining the capability to provide full functionality when needed, thereby managing thermal output more effectively.
Data Source
AI summary
A processor for a portable electronic device. The processor includes a RISC (reduced instruction set computing) core a CISC (complex instruction set computing) core, a video accelerator circuit and an audio accelerator circuit. Each of the video and audio accelerator circuits are coupled to both the RISC and CISC cores, with both cores and both accelerator circuit being incorporated into a single integrated circuit. In a first plurality of operational modes, the RISC core is active, while the CISC core is in one of a sleep state or a power off state. In a second plurality of modes, both the RISC and CISC cores are active.


