Dual-Core Processor with Shaves for Real-Time Object Detection

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Solution Overview

Problem

Current face detection technologies in mobile devices face challenges with slow performance, high power consumption, and difficulty in meeting hard real-time requirements due to the computational intensity of deep learning algorithms, especially when running on serial processors without parallel computing co-processors like GPUs, and are limited by mobile operating systems not designed for low latency.

Innovation Solution

A processor architecture with two CPU cores and multiple shaves is used, where one CPU core handles general tasks and the other schedules computation tasks for object-detection models across the shaves, enabling parallel processing and dynamic task management to achieve real-time face detection with improved energy efficiency and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If deep learning algorithms are used for face detection, then detection accuracy is improved, but processing speed deteriorates due to computational intensity on serial processors

Engineering Contradiction:
Improvedetection accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The processor is divided into multiple specialized cores: first CPU core for general tasks, second CPU core for deep learning computation, and multiple shaves for parallel image processing. This segmentation allows each core to be optimized for its specific function, enabling deep learning algorithms to run faster by distributing computational load across multiple specialized units rather than a single serial processor

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from traditional single-core serial processing to a multi-dimensional parallel processing architecture. Image frames are divided into multiple partitions that can be processed simultaneously by different shaves, adding a spatial dimension to computation. This dimensional expansion from serial to parallel processing fundamentally changes the computational throughput capability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If deep learning algorithms are used for face detection, then detection accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvedetection accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The processing workload is segmented across multiple specialized cores, allowing the system to perform deep learning computations more efficiently. By dedicating specific cores to specific tasks (second CPU core for deep learning, multiple shaves for parallel processing), the system reduces overall power consumption compared to running all computations on a single general-purpose core, as each specialized core can be optimized for energy efficiency in its specific function

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements dynamic task scheduling where the second CPU core periodically assigns computation tasks to available shaves based on current system state and workload. This periodic task distribution allows the system to balance computational throughput with power consumption by activating only the necessary processing units when needed, rather than maintaining constant high-power operation

Inventive Principle:
Principle #19Periodic action

3Loss of time

If computational resources are allocated to satisfy real-time face detection requirements, then detection latency is reduced, but other CPU tasks experience performance degradation

Engineering Contradiction:
Improvedetection latencyVSAvoidgeneral CPU task performance
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The processor is segmented into dedicated functional units: the first CPU core handles general CPU tasks, while the second CPU core and multiple shaves are dedicated to face detection. This segmentation isolates the high-computation face detection workload from general CPU tasks, ensuring that real-time detection requirements do not degrade the performance of other system tasks, as each core operates independently with its own task queue

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second CPU core acts as an intermediary between the camera sensor/input stream and the parallel shave processors. It receives image frames, prepares computation tasks, distributes them to appropriate shaves, and aggregates results. This intermediary role allows efficient coordination of real-time detection without interfering with the first CPU core's handling of general tasks, maintaining system-wide productivity while achieving low-latency detection

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11741568B2Systems and methods for low-power, real-time object detection
Publication Date: 2023.08.29 BAIDU USA LLC
  • US11741568B2 patent drawing
  • US11741568B2 patent drawing
  • US11741568B2 patent drawing

AI summary

Described herein are systems and methods for object detection to achieve hard real-time performance with low latency. Real-time object detection frameworks are disclosed. In one or more embodiments, a framework comprises a first CPU core, a second CPU core, and a plurality of shaves. In one or more embodiments, the first CPU core handles general CPU tasks, while the second CPU core handles the image frames from a camera sensor and computation task scheduling. In one or more embodiments, the scheduled computation tasks are implemented by the plurality of shaves using at least one object-detection model to detect an object in an image frame. In one or more embodiments, computation results from the object-detection model with a higher detection probability is used to form an output for object detection. In one or more embodiments, the object-detection models share some parameters for smaller size and higher implementing speed.