Dual-Core SSD Controller Parallel Host and Flash Data Paths
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Solution Overview
Problem
Current solid state drive (SSD) controllers with a single core are limited in performance due to the restriction of processing multiple operations sequentially or simultaneously, and the increasing number of channels further exacerbates this limitation, hindering efficient data transmission and storage.
Innovation Solution
A dual-core memory controller architecture is introduced, where the first core manages data transmission with the host and the second core handles data with the flash memories, utilizing a queue manager system to distribute and balance command processing between the cores based on threshold comparisons, allowing for parallel communication and load balancing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-core controller is used, then the device complexity is low, but the processing performance and productivity are limited due to sequential operation constraints
Solution Approach 1:
The controller is segmented into two independent cores: a first core for managing host interface and data transmission, and a second core for managing flash memory operations. This segmentation allows parallel processing of host commands and memory operations, resolving the productivity limitation of single-core sequential processing while maintaining manageable complexity through functional separation.
Solution Approach 2:
The system transitions from single-dimensional sequential processing to two-dimensional parallel processing by introducing a second core that operates independently from the first core. This dimensional expansion enables simultaneous execution of host interface management and flash memory control, dramatically improving processing throughput.
2Productivity
If the number of channels is increased, then the data transmission capacity is improved, but the single-core controller becomes a bottleneck hindering efficient data transmission
Solution Approach 1:
With multiple channels (e.g., four channels) connected to flash memories, the system segments channel management between two cores. The first core handles host interface operations while the second core manages flash memory channel operations, enabling efficient parallel data transmission across multiple channels without single-core bottlenecks.
3Productivity
If a dual-core architecture is implemented, then parallel communication and load balancing are enabled, but the device complexity increases
Solution Approach 1:
The dual-core architecture segments control functions into distinct operational domains: the first core manages host interface layer, cache allocation layer, and receives host commands, while the second core manages flash translation layer and flash interface layer. This functional segmentation enables parallel communication with host and memory device simultaneously, achieving load balancing while keeping each core's complexity manageable through clear functional boundaries.
Data Source
AI summary
The solid state drive device includes a memory device including a plurality of flash memories and a memory controller connected with a host and configured to control the memory device. The memory controller includes first and second cores, a host interface configured to interface with the host, and a flash memory controller configured to control the plurality of flash memories. The first core is configured to control transmission and reception of data to and from the host. The second core is configured to control transmission and reception of data to and from the memory device.