Dual-Counter Frequency Divider for High Ratios and Duty Cycle Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional frequency dividers, such as pulse swallow dividers and single high speed counter dividers, face limitations in achieving symmetric duty cycles and high division ratios due to the need for additional circuits and power consumption, particularly when dealing with odd division ratios and multiple output frequencies.
Innovation Solution
A method and device utilizing a high speed counter and a low speed counter with adjustable duty cycles and phase offsets, where the high speed counter determines the output signal frequency by counting cycles and the low speed counter extends the counting capacity to achieve high division ratios and symmetric or asymmetric duty cycles, with an optional duty cycle adjustment arrangement to correct uneven duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a pulse swallow divider architecture is used, then high frequency division is achieved, but the output duty cycle becomes asymmetric and additional correction circuits are required
Solution Approach 1:
The frequency division function is segmented into two independent counters: a first counter handling high-frequency prescaling and a second counter handling lower-frequency division. This segmentation allows each counter to operate optimally in its frequency range without requiring complex interaction circuits, thereby reducing overall device complexity while maintaining high frequency division capability.
Solution Approach 2:
The patent transitions from a single-dimensional prescaler architecture to a two-dimensional counter architecture by introducing a second counter that operates at a different frequency dimension. This dimensional change enables symmetric duty cycle generation through independent counting operations, eliminating the need for additional duty cycle correction circuits.
2Device complexity
If a single high speed counter is used, then circuit complexity is reduced, but the maximum division ratio is limited by counter speed
Solution Approach 1:
The counting function is divided between two counters with different speed characteristics. The first counter handles the high-speed prescaling portion of the division ratio, while the second counter handles the remaining lower-frequency division. This segmentation allows the system to achieve very high overall division ratios without requiring a single ultra-high-speed counter, thus maintaining circuit simplicity while expanding adaptability.
3Manufacturing precision
If additional duty cycle correction circuits are added, then symmetric duty cycle is achieved, but device complexity increases
Solution Approach 1:
Instead of adding correction circuits to fix duty cycle asymmetry, the patent introduces a second counter operating in a different frequency dimension. This second counter independently generates symmetric clock phases, naturally producing a symmetric duty cycle output without requiring any additional correction logic or complex timing adjustment circuits.
Data Source
AI summary
A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.