Dual CPU Core Architecture for Fast Module Activation
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Solution Overview
Problem
Existing information processing devices with sequentially activated modules face a long activation time, which can be mitigated by increasing CPU operation speed, but this results in higher power consumption.
Innovation Solution
The implementation of a dual CPU core configuration, where a first CPU core with a lower operating frequency performs initial verification processes and a second CPU core with a higher operating frequency handles subsequent verification processes, while maintaining a program storage section for storing modules and their electronic signatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the CPU operation speed is increased to shorten activation time, then the activation time is reduced, but the power consumption amount is increased
Solution Approach 1:
The system divides the CPU functionality into multiple CPU cores with different operating frequencies. A first CPU core operates at a lower frequency for initial module activation, while a second CPU core operates at a higher frequency for subsequent module activations. This segmentation allows the system to optimize power consumption by using lower power for initial operations and only deploying higher power resources when needed for time-critical operations.
Solution Approach 2:
Different CPU cores are assigned different operating frequencies based on the specific requirements of the modules they execute. The first CPU core uses a lower operating frequency suitable for the initial module, while the second CPU core uses a higher operating frequency for subsequent modules that require faster processing. This local quality approach ensures that power consumption is optimized for each specific operational context.
2Reliability
If multiple modules are sequentially activated for verification, then security is ensured through signature verification, but the activation time is prolonged
Solution Approach 1:
The module activation process is segmented into multiple phases, each handled by appropriate CPU cores. The first CPU core handles the initial module activation with full security verification, while subsequent modules are activated by the second CPU core which operates at higher speed. This segmentation maintains security requirements while reducing the time penalty of sequential verification.
Solution Approach 2:
The system dynamically switches between different CPU cores based on the activation stage. The first CPU core is used for initial module activation, and after that module is activated, the system transitions to using the second CPU core for subsequent module activations. This dynamic approach allows the system to adapt its processing speed to the specific requirements of each activation stage, maintaining security while improving overall activation time.
Data Source
AI summary
An information processing device includes a first CPU core; a second CPU core having an operating frequency higher than that of the first CPU core; and a program storage section configured to store a first module, a second module, a third module having a capacity size larger than that of the second module, a second module electronic signature, and a third module electronic signature, wherein the first CPU core is configured to, by executing the first module, perform a second module verification process of verifying the second module based on the second module electronic signature and the second CPU core is configured to, by executing the second module, perform a third module verification process of verifying the third module based on the third module electronic signature.