Dual-CPU Debug Synchronization Using Triggered Memory Writes
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Solution Overview
Problem
Existing debugging techniques for multiprocessor systems with two CPUs cannot synchronize memory operations across both CPUs, limiting the ability to perform synchronized debugging.
Innovation Solution
An operation verifying program is installed on two semiconductor devices that communicate with each other, analyzing and synchronizing operation verifying commands to output trigger signals and write memory setting values at synchronized timings, enabling synchronized operation restarts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If debugging is performed using existing multiprocessor system techniques, then one CPU can be debugged, but memory operations cannot be synchronized across both CPUs
Solution Approach 1:
A trigger signal serves as an intermediary mechanism between the first and second CPUs. The first CPU outputs a trigger signal that the second CPU receives and analyzes, using this signal to synchronize memory write operations. This mediator enables coordinated debugging across both CPUs without requiring complex direct communication protocols.
Solution Approach 2:
The system implements a feedback mechanism where the second CPU analyzes the received trigger signal and responds by synchronizing its memory operations with the first CPU. This feedback loop ensures that both CPUs perform memory operations at synchronized timings, allowing reliable debugging of multiprocessor systems.
2Ease of operation
If memory operations are performed independently on two CPUs, then each CPU can operate autonomously, but synchronized debugging cannot be achieved
Solution Approach 1:
The trigger signal acts as a simple intermediary that maintains CPU autonomy while enabling synchronization. Each CPU independently processes the trigger signal according to its own instruction set, preserving autonomy. The synchronization mechanism remains relatively simple because it relies on this single intermediary signal rather than complex inter-CPU coordination protocols.
3Extent of automation
If debugging commands are transferred between CPUs, then one CPU can control debugging of the other, but simultaneous memory operation at synchronized timing cannot be achieved
Solution Approach 1:
The system uses feedback where the second CPU analyzes the trigger signal and adjusts its memory operation timing accordingly. This feedback mechanism ensures that memory writes occur at synchronized timings while maintaining automated debugging control. The first CPU's debug commands are automatically transferred and executed with precise timing coordination.
Data Source
AI summary
In the conventional semiconductor device, it is impossible for two CPUs to operate memories to be debugged at synchronous timings. According to one embodiment, the operation verifying program analyzes the operation verifying command received by the first semiconductor device 10 from the external device 31 by its own device (S32), transfers the operation verifying command to the second semiconductor device 20 (S31, S41), also analyzes the operation verifying command in the second semiconductor device 20 (S42), outputs the trigger signal (S34, S44) to the first semiconductor device 10 from the second semiconductor device 20 based on the result of the analysis, writes the memory setting values included in the operation verifying command to the memories in the respective semiconductor device (S35, S45) based on the trigger signal, and restarts the device operation based on the written memory setting values.