Dual-CPU Comparator Circuit for Early Semiconductor Failure Prediction
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Solution Overview
Problem
Existing semiconductor devices lack the ability to predict and adapt to failure locations, as they do not have a function to identify specific failure points within the device, leading to ineffective operation changes during abnormal conditions.
Innovation Solution
A semiconductor device comprising a first circuit, a second circuit with a comparable configuration but different operating margins, and a comparator to detect mismatches in output signals, allowing for predictive maintenance and operation adjustments based on detected failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an independent evaluation circuit is used to detect deterioration, then detection capability is improved, but the ability to identify specific failure locations deteriorates
Solution Approach 1:
The invention divides the monitoring function into multiple segments: the evaluation circuit detects deterioration, while the tag circuit identifies the specific failure location. This segmentation allows both detection capability and location information to be preserved simultaneously.
Solution Approach 2:
The tag circuit acts as an intermediary that links the evaluation circuit's detection function with the main body circuit's operational function. When deterioration is detected, the tag circuit provides location information that enables targeted operational changes without requiring the evaluation circuit to directly control the main body.
2Reliability
If operation changes are made based on general deterioration detection, then device reliability is improved, but the ability to adapt to specific failure locations deteriorates
Solution Approach 1:
The system segments the response mechanism into two parts: the evaluation circuit provides general deterioration detection for reliability, while the tag circuit provides specific location information for adaptability. This allows operation changes to be tailored to specific failure locations rather than applying generic responses.
Solution Approach 2:
The tag circuit is pre-configured with identification information for different failure locations before deterioration occurs. When the evaluation circuit detects deterioration, the pre-prepared tag information enables immediate adaptation to the specific failure location, improving both reliability and adaptability.
3Device complexity
If a simple deterioration detection system is used, then device complexity is reduced, but the ability to predict and respond to specific failures deteriorates
Solution Approach 1:
The tag circuit is a simplified copy or counterpart to the evaluation circuit, designed specifically for identification rather than complex detection. This copying approach adds minimal complexity while providing precise failure location information that enhances prediction accuracy.
Solution Approach 2:
The tag circuit serves multiple functions: it identifies failure locations, provides prediction information, and enables targeted operational changes. This multi-functionality achieves high prediction precision without requiring a proportionally complex system architecture.
Data Source
AI summary
A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of the first CPU with an output of the second CPU. The second CPU is made so as to have a lower operating margin than the first CPU. By supplying a same signal to the first CPU and the second CPU and then detecting a mismatch between the outputs of the first CPU and the second CPU as a result of comparison, the abnormality is predicted. The semiconductor device includes a reset control circuit that resets the device when the result of comparison by the comparator indicates an error.