Dual-CPU Interface Control Mechanism for Concurrent LBA and Key-Value Processing
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Solution Overview
Problem
Modern operating systems are limited by a fixed 512-byte block size for data storage, leading to inefficiencies and performance degradation in large database operations, particularly in clustered computing environments, where error recovery processes are complex and performance is severely impacted.
Innovation Solution
An electronic system with an interface control mechanism that includes two CPUs to process logical block address (LBA) and key-value commands independently and concurrently, allowing for efficient data management and bypassing the traditional I/O storage stack, enabling larger data transfers and supporting both LBA and key-value architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed 512-byte block size is used for data storage, then compatibility with traditional operating systems is maintained, but data management efficiency and performance degrade in large database operations
Solution Approach 1:
The patent divides the storage interface into two independent processing paths: one for traditional LBA commands and another for key-value commands. This segmentation allows the system to simultaneously support fixed block sizes for OS compatibility while enabling efficient large-block operations through the key-value interface, resolving the contradiction between compatibility and performance.
Solution Approach 2:
The patent introduces a new key-value command interface as an additional dimension alongside the traditional LBA interface. This allows data to be accessed through two different paradigms: the conventional fixed-block LBA method for compatibility, and the efficient key-value method for high-performance operations, thereby resolving the performance limitation without sacrificing compatibility.
2Productivity
If larger internal data block sizes (1K to 4K bytes) are used, then data transfer efficiency improves, but error recovery complexity and performance degradation increase
Solution Approach 1:
The patent introduces a key-value interface as an intermediary layer between the host and the storage device's internal large blocks. This intermediary allows efficient large-block transfers without requiring the host to directly manage the complexity of error recovery, as the key-value interface abstracts these complexities while maintaining simple update operations.
3Reliability
If single block updates are executed as read-modify-write operations, then data integrity is maintained, but performance severely degrades
Solution Approach 1:
The patent extracts the read-modify-write complexity from the update operation by introducing incremental updates through the key-value interface. Instead of requiring full read-modify-write cycles, the system allows direct updates to be issued and applied incrementally, maintaining data integrity while dramatically improving update performance.
4Productivity
If a dual CPU architecture is implemented to process LBA and key-value commands concurrently, then execution performance improves, but device complexity increases
Solution Approach 1:
The patent segments the command processing function into two independent CPU units: one dedicated to LBA commands and another to key-value commands. This segmentation enables concurrent processing of both command types without requiring complex coordination or context switching, thereby improving performance while keeping the architecture relatively simple through functional separation.
Data Source
AI summary
An electronic system includes: a storage device, configured to receive an interface command including: an interface control unit, a first CPU, coupled to the interface control unit, configured to execute a logical block address (LBA) command, a second CPU, coupled to the interface control unit, configured to execute a key-value command, and a non-volatile storage, coupled to the volatile memory, the first CPU, and the second CPU configured to process the LBA command and the key-value command independently and concurrently; wherein: the first CPU or the second CPU are configured to compile a detailed status after completing the LBA command or the key-value command; and the interface control unit, connected to a device coupling structure, is configured to respond to the interface command by sending the detailed status to a device driver.