Dual CPU Power Failure Detection via CPLD Logic
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Solution Overview
Problem
Existing methods for detecting power failures in central processing units (CPUs) are time-consuming and inefficient, particularly when checking the power module, as they require sequential measurements with tools like oscilloscopes or power meters.
Innovation Solution
A power failure detecting system comprising a dual CPU setup with a complex programmable logic device (CPLD) that communicates between CPUs, a power controlling unit, a platform controller hub (PCH), and a baseboard management controller (BMC), which determines power failures and controls power supply to individual CPUs, allowing for faster detection and potential power restarts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential measurement with oscilloscope or power meter is used to check power module, then measurement accuracy is maintained, but detection time increases significantly
Solution Approach 1:
The patent creates a virtual copy of the power measurement function through software simulation. The power failure detection system uses a power failure detection program that simulates the measurement process, allowing the system to detect power module status without physical sequential measurement. This virtual copying enables parallel detection of multiple power parameters simultaneously, resolving the contradiction between measurement accuracy and detection time.
Solution Approach 2:
The patent replaces the mechanical measurement system (oscilloscope, power meter) with an electronic/software-based detection system. Instead of using physical measurement tools that require sequential connection and measurement, the system uses electronic signals and software algorithms to detect power module status. This substitution eliminates the time-consuming sequential measurement process while maintaining detection capability through electronic monitoring of power good signals and other power parameters.
2Difficulty of detecting and measuring
If manual measurement tools are used for power failure detection, then detection capability is achieved, but operational complexity increases
Solution Approach 1:
The patent implements self-service detection where the system automatically monitors and detects power failures without requiring manual intervention. The power failure detection program continuously checks power module status, and the system automatically identifies power failures and generates alerts. This eliminates the need for operators to manually connect measurement tools and perform sequential checks, significantly reducing operational complexity while maintaining comprehensive detection capability.
Solution Approach 2:
The patent establishes a feedback mechanism where the system continuously monitors power parameters and automatically responds to detected anomalies. The power failure detection system receives feedback from power good signals and other power sensors, processes this information through the detection program, and generates appropriate responses. This automated feedback loop simplifies operation by eliminating manual measurement steps while ensuring comprehensive power failure detection through continuous monitoring and automatic analysis of power system status.
Data Source
AI summary
A system for detecting power failure in a dual processing system includes a first central processing unit (CPU), a second CPU, a power controlling unit, and a complex programmable logic device (CPLD). The power controlling unit is electrically coupled to the first CPU and the second CPU and the CPLD. The CPLD can determine a power failure occurring in relation to the first CPU and the second CPU. If power to the first CPU does not fail but power to the second CPU does fail, the CPLD controls the power controlling unit to stop supplying power for the second CPU only and make a certain number of power restart attempts. A method for detecting a power failure is also provided.