Dual DAC Charge-Redistribution ADC for Faster Low-Power Bit Trials
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Solution Overview
Problem
Charge redistributed Analog to Digital Converters (ADCs) face challenges with high power consumption and slow operation due to large capacitors and switch devices required for noise-dominated high-resolution applications, which affect their efficiency and speed.
Innovation Solution
The implementation of a dual or single DAC structure with a small and large capacitor array, where the small DAC handles the most significant bit positions and the large DAC handles the least significant bit positions, along with a bridging switch and redundant capacitor for error correction, reduces power consumption and increases speed by minimizing the need for large capacitors and switches to be charged and discharged during bit trials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large capacitors are used in charge redistributed ADCs to reduce noise, then measurement precision is improved, but power consumption increases and operation speed decreases
Solution Approach 1:
The patent divides the capacitor array into two separate DAC structures: a first DAC with smaller capacitors and a second DAC with larger capacitors. This segmentation allows the system to use smaller capacitors for MSB conversions (reducing power consumption) while reserving larger capacitors for LSB conversions where higher precision is needed, thus resolving the contradiction between power consumption and measurement precision.
2Measurement precision
If large capacitors are used in charge redistributed ADCs to reduce noise, then measurement precision is improved, but operation speed decreases
Solution Approach 1:
The patent segments the conversion process into two phases: MSB conversion using the first DAC with smaller capacitors (faster operation) and LSB conversion using the second DAC with larger capacitors (higher precision). This segmentation resolves the contradiction by allowing fast operation where speed is critical and high precision where accuracy is critical.
Solution Approach 2:
The patent performs MSB conversions first using the smaller-capacitor DAC before proceeding to LSB conversions with the larger-capacitor DAC. This preliminary action allows the system to quickly resolve the most significant bits that determine the overall magnitude, then refine with higher precision for less significant bits, optimizing both speed and precision.
3Reliability
If large switch devices are used to control large capacitors, then reliability is improved, but power consumption increases and settling time increases
Solution Approach 1:
The patent segments the switch control requirements by assigning smaller switches to the first DAC (for MSB) and larger switches to the second DAC (for LSB). This segmentation reduces power consumption and settling time for the majority of conversion operations (MSB) while maintaining reliability for critical precision operations (LSB).
Data Source
AI summary
A system for converting an analog signal to a digital codeword having N bit positions that includes a dual DAC structure having a small DAC and a large DAC. At least one comparator is coupled to the small DAC and large DAC. The small DAC performs bit trials to calculate bit positions 1 to M, and the large DAC with performs bit trial calculates bit positions M+1 to N after having been set with bit decisions from the bit trials of the small DAC.