Dual-DAC SAR ADC Correction for Accurate Bit Determination
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Solution Overview
Problem
Successive-approximation type A/D conversion circuits face accuracy issues due to rapid charging and discharging cycles, leading to voltage differences in comparison reference signals, which can result in erroneous bit determination and decreased digital output signal accuracy.
Innovation Solution
The proposed analog-digital conversion circuit employs a dual D/A converter system with capacitive elements and a correction circuit to generate a sum of weighted reference signals, ensuring accurate bit determination by overlapping comparison ranges and utilizing redundancy to correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the charging and discharging cycle period decreases to speed up A/D conversion, then conversion speed increases, but the capacitor cannot be sufficiently charged or discharged leading to voltage differences and erroneous determination
Solution Approach 1:
The patent divides the single capacitor into multiple capacitors (first capacitor and second capacitor) with different capacitance values. Each capacitor handles different bit comparisons, allowing parallel charging/discharging operations that maintain sufficient charge time while increasing overall conversion speed
Solution Approach 2:
The patent pre-charges or pre-discharges capacitors to specific voltage levels before comparison operations begin. This preliminary action ensures that when the comparison starts, the capacitors are already at the correct voltage states, eliminating the need for slow charging/discharging during the comparison cycle itself
2Loss of time
If the capacitor charges or discharges rapidly to meet speed requirements, then conversion time decreases, but voltage differences cause erroneous bit determination
Solution Approach 1:
The patent introduces a correction circuit as an intermediary that detects voltage differences caused by rapid charging/discharging and compensates for them. This correction circuit calculates correction values based on the voltage differences and adjusts the comparison results accordingly, maintaining reliability while enabling faster conversion
Solution Approach 2:
The patent implements a feedback mechanism where the correction circuit continuously monitors the voltage differences across capacitors during rapid charging/discharging cycles and dynamically adjusts correction values. This feedback loop ensures that even as conversion speed increases, the system maintains accurate bit determination by compensating for voltage deviations in real-time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of the digital output signal by suppressing large changes in comparison reference signals and preventing erroneous determinations, thereby improving the overall precision of the A/D conversion process.
Implementation Method 1
a first capacitive element (16) and a second capacitive element (17) are respectively connected to output terminals of the first digital-analog converter (14) and the second digital-analog converter (15)
Data Source
AI summary
An analog-digital conversion circuit includes a comparator that receives an analog input signal. A controller generates an N1-bit first signal and an N2B-bit second signal in accordance with an output signal from the comparator. A first digital-analog converter generates a first reference signal from the first signal. A second digital-analog converter generates a second reference signal from the second signal. A correction circuit corrects the first and second signals to generate a digital output signal. The N2B-bit second signal is acquired by adding a Kbit correction signal to an N2A-bit signal. The controller sequentially sets bit values of the first signal and bit values of the second signal in accordance with the output signal of the comparator. The correction circuit generates the (N1+N2A)-bit digital output signal based on a sum of a value acquired by multiplying the N1-bit first signal by 2^N2A and a value of the N2B-bit second signal.