Dual-DAC Signal Generation With Frequency Shifting for Wider Bandwidth
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Solution Overview
Problem
Current high-speed digital-to-analog converters (DACs) have insufficient output bandwidth, limiting the capacity and functionality of communication systems, and existing techniques for increasing bandwidth through time-interleaved DACs do not effectively address the issue of asymmetric circuit configurations and require complex adjustments.
Innovation Solution
A signal generating device using two DACs with a digital signal processing unit that alternately switches their outputs through an analog multiplexer, shifting frequency components to achieve a broader bandwidth without requiring complex adjustments, and includes compensation for response characteristics and low-pass filtering to suppress high-frequency components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved DACs are used to increase sampling rate, then productivity is improved, but device complexity increases due to asymmetric circuit configurations and complex adjustments
Solution Approach 1:
The patent applies asymmetry by intentionally introducing a delay to one of the DAC output signals to create an asymmetric time-interleaved configuration. This asymmetric design allows the combined output to achieve higher effective sampling rates while managing the complexity through controlled asymmetry rather than requiring complex adjustment mechanisms
Solution Approach 2:
The patent applies preliminary action by pre-compensating for the asymmetric delay introduced in the time-interleaved DAC configuration. A compensation filter is applied to one of the DAC outputs before combination to counteract the timing mismatch, thereby simplifying the overall system adjustment while maintaining high productivity
2Productivity
If multiple DACs are combined using adder, then productivity is improved through higher sampling rate, but the output bandwidth remains limited to individual DAC bandwidth
Solution Approach 1:
The patent applies dimensionality change by transitioning from simple time-domain interleaving to a combined time-frequency domain approach. By introducing frequency-dependent phase compensation and utilizing asymmetric delay configurations, the system effectively expands the output bandwidth beyond the individual DAC limitations while maintaining high sampling rates
3Speed
If asymmetric DAC configuration is used to broaden bandwidth, then output bandwidth is improved, but ease of operation deteriorates due to complicated phase and amplitude adjustments
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-configuring the compensation filters to match the specific asymmetric delay introduced in the system. This pre-compensation approach eliminates the need for complex real-time adjustments of phase and amplitude, thereby maintaining broad bandwidth while significantly improving ease of operation
Solution Approach 2:
The patent applies self-service by designing the asymmetric time-interleaved DAC system with built-in self-compensation mechanisms. The compensation filters are automatically configured based on the known delay characteristics, allowing the system to self-adjust without requiring external complex calibration procedures
Data Source
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AI summary
A DAC on a conventional CMOS platform has an analog output bandwidth of about 15 GHz, which is insufficient and causes one of bottlenecks in realizing the increase of capacity for communication systems. In the conventional technique, only an output having a bandwidth identical to the bandwidth of individual DACs has been obtained even by using a plurality of DACs. Also, even when the output of a bandwidth broader than the individual DAC is obtained, there has been a problem associated with asymmetricity of a circuit configuration. In a signal generating device of the present invention, a plurality of normal DACs are combined to realize an analog output of a broader bandwidth beyond the output bandwidth of the individual DACs, and the problem of the asymmetricity of the circuit configuration is also resolved. A desired signal is separated into a low-frequency signal and a high-frequency signal in a frequency domain, and a series of operation of constant (r)-folding the amplitude of the high-frequency signal and shifting it on the frequency axis to superimpose it on the low-frequency signal are made in a digital domain. The output of each DAC is switched by an analog multiplexer. A configuration example adapted to occurrence of a multicarrier signal is also disclosed.