Dual-DAC Self-Test Circuit Using Offset Ramp Comparison
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Solution Overview
Problem
The existing methods for testing digital to analog conversion circuits are time-consuming, requiring lengthy test routines that impact global device costs and efficiency, especially in smart power devices with complex A/D conversion structures.
Innovation Solution
An electronic circuit and method that includes two digital to analog converters coupled to sign comparators through a switch network, using ramp generation and evaluation circuits to automatically test DAC integrity by shifting digital code ramps and issuing a go/no-go signal based on comparator outputs, allowing for faster and more efficient self-testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long test routine is used to test all possible stimuli via communication protocol and pin remap, then comprehensive test coverage is achieved, but test time increases significantly
Solution Approach 1:
The patent implements self-test functionality where the DAC circuit tests itself by comparing its own output across different channels, eliminating the need for external test equipment and lengthy communication protocols. The circuit uses its internal resources (comparators, switch network) to perform comprehensive testing autonomously, achieving both complete coverage and reduced test time.
Solution Approach 2:
The patent merges multiple test functions into a single integrated self-test routine. By combining the DAC output comparison across channels, the switch network routing, and the comparator evaluation into one unified test mechanism, the system achieves comprehensive testing without requiring separate test procedures for each function, thereby reducing overall test time while maintaining complete coverage.
2Measurement precision
If external test equipment is used to measure DAC output, then accurate measurement is achieved, but test complexity and cost increase
Solution Approach 1:
The patent eliminates external test equipment by implementing self-test functionality where the circuit uses its own internal comparators and switch network to measure and evaluate DAC outputs. The comparators directly compare DAC outputs against reference levels, providing accurate measurement without external instruments, thereby reducing test complexity and cost while maintaining measurement precision.
Solution Approach 2:
The patent makes the DAC circuit multi-functional by enabling it to perform both its primary conversion function and self-testing function using the same hardware resources. The switch network and comparators serve dual purposes: normal operation and self-test measurement, eliminating the need for dedicated external test equipment and reducing overall system complexity.
3Reliability
If all digital codes are applied sequentially via communication protocol, then complete DAC testing is achieved, but test time becomes very long
Solution Approach 1:
The patent implements self-test functionality where the DAC circuit tests itself by comparing its own output across different channels, eliminating the need for external test equipment and lengthy communication protocols. The circuit uses its internal resources (comparators, switch network) to perform comprehensive testing autonomously, achieving both complete coverage and reduced test time.
Solution Approach 2:
The patent merges multiple test functions into a single integrated self-test routine. By combining the DAC output comparison across channels, the switch network routing, and the comparator evaluation into one unified test mechanism, the system achieves comprehensive testing without requiring separate test procedures for each function, thereby reducing overall test time while maintaining complete coverage.
Data Source
AI summary
An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.