Dual-DAC SAR ADC Code Swapping for Settling Accuracy
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Solution Overview
Problem
SAR ADCs face issues with improper settling of reference voltages leading to setting errors and insufficient settling times, which affect accuracy and resolution.
Innovation Solution
The proposed solution involves a SAR ADC with a first and second DAC to adjust signal levels at nodes based on input analog signals, a comparator to compare these levels, and a controller to generate digital values during a conversion phase, with a code swap circuit to swap digital values between DACs during sampling phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional SAR ADC uses a single DAC and standard sampling phase, then the device complexity is low, but settling errors occur and measurement precision deteriorates
Solution Approach 1:
The patent divides the single DAC into two separate DACs (first DAC and second DAC), each handling different input analog signals (first input analog signal and second input analog signal). This segmentation allows independent optimization of each DAC's settling process and enables parallel processing, thereby improving measurement precision while managing complexity through modular architecture.
Solution Approach 2:
The patent introduces a dual-phase sampling mechanism where the first DAC processes the first input analog signal during one sampling phase, and the second DAC processes the second input analog signal during another sampling phase. This periodic action with alternating phases allows each DAC sufficient settling time while maintaining overall system throughput, resolving the contradiction between precision and complexity.
2Measurement precision
If the SAR ADC uses insufficient settling time, then the productivity is high, but setting errors increase and measurement precision worsens
Solution Approach 1:
The patent implements continuous conversion operation by overlapping the sampling phases of the two DACs. While the first DAC is settling during its sampling phase, the second DAC is simultaneously sampling, and vice versa. This continuity ensures that one DAC is always in the conversion phase, maintaining high productivity while each DAC enjoys sufficient settling time during its dedicated phase.
Solution Approach 2:
By using alternating sampling phases for the two DACs, the system achieves periodic operation where each DAC gets adequate settling time in its own phase while the overall conversion process continues without interruption. This periodic alternation resolves the conflict between settling time requirements and conversion speed.
3Measurement precision
If the reference voltage does not settle properly before comparison, then the conversion time is short, but setting errors occur and measurement precision deteriorates
Solution Approach 1:
The patent segments the voltage settling process by assigning separate settling periods to the first DAC and second DAC in different sampling phases. Each DAC can settle its reference voltage independently without interfering with the other, ensuring proper settling for each while maintaining overall conversion efficiency.
Solution Approach 2:
The patent performs preliminary settling of reference voltages during dedicated sampling phases before the actual comparison operation. The first DAC settles during the first sampling phase, and the second DAC settles during the second sampling phase, ensuring that both are fully settled before their respective comparisons, thereby eliminating setting errors.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) configured to change a signal level of a first node based on a first and second input analog signals, a second DAC configured to change a signal level of a second node based on one of the first input analog signal and the second input analog signal, a comparator configured to compare the signal level of the first node and the signal level of the second node, and a controller configured to generate a first digital value for the first DAC and a second digital value for the second DAC based on an output of the comparator during a first conversion phase corresponding to a first sampling phase, input the first digital value into the second DAC before a second sampling phase, and input the second digital value into the first DAC before the second sampling phase.