Dual Damascene Cap Layer Removal via CF4/NF3 Plasma
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The misalignment between via openings and lower copper wiring in semiconductor manufacturing leads to undesired recess defects during the liner removal step, affecting the uniform deposition of barrier layers and reliability of integrated circuit devices, and the use of hydrogen-containing gases like CH2F2 or CHF3 results in difficult-to-remove residues.
Innovation Solution
A dual damascene process using CF4/NF3 plasma for selective removal of the cap layer, ensuring minimal etching of the underlying low-k dielectric layer and preventing recess defects, with a step height control of less than 150 angstroms to facilitate uniform barrier deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hydrogen-containing gases (CH2F2 or CHF3) are used for cap layer removal, then the cap layer can be selectively removed, but residues are formed that are difficult to remove
Solution Approach 1:
The patent changes the chemical composition parameters of the plasma etching gas from hydrogen-containing gases (CH2F2, CHF3) to hydrogen-free carbon fluoride gas (CF4). This parameter change eliminates the formation of difficult-to-remove residues while maintaining effective cap layer removal through adjustment of etching conditions
Solution Approach 2:
The patent converts the previously harmful effect of residue formation into a beneficial outcome by using CF4 plasma, which inherently prevents residue formation. The hydrogen-free composition of CF4 plasma eliminates carbon-hydrogen bond formation that causes residues, turning a problematic process into a clean etching method
2Manufacturing precision
If misalignment between via opening and lower copper wiring occurs, then via opening can be formed, but recess defects are etched into the low-k dielectric layer
Solution Approach 1:
The patent applies preliminary protective action by using CF4 plasma with controlled etching parameters to prevent excessive etching of the low-k dielectric layer before recess defects can form. The process is designed to stop etching once the cap layer is removed, preventing the via opening from etching into the dielectric layer even when misalignment occurs
Solution Approach 2:
The patent changes the plasma chemistry from hydrogen-containing to hydrogen-free CF4, which alters the etching characteristics to be more selective and controllable. This parameter change allows precise removal of the cap layer while automatically limiting further etching into the low-k dielectric layer, preventing recess defect formation
3Manufacturing precision
If via opening is etched through misalignment, then opening can be formed, but uniform barrier deposition is prevented
Solution Approach 1:
The patent prevents the creation of problematic step heights at the via opening bottom by controlling the etching process to stop precisely at the cap layer interface. By preventing excessive etching into the low-k dielectric layer, the surface remains relatively flat, ensuring uniform barrier layer deposition in subsequent processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively addresses misalignment issues by preventing recess defects and ensuring uniform barrier deposition, improving the reliability and performance of semiconductor devices while eliminating residue problems associated with hydrogen-containing gases.
Implementation Method 1
A liner removal step is performed by employing CF4/NF3 plasma to selectively remove the exposed cap layer from the opening
Implementation Method 2
CF4/NF3 plasma for selective removal of the cap layer
Data Source
AI summary
A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.