Dual Damascene Interconnect Openings With Multi-Layer Etch Masks
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Solution Overview
Problem
The semiconductor industry faces challenges in forming accurate and efficient interconnect openings in dielectric materials during the dual damascene process, particularly due to issues with etching selectivity and distortion of interconnect openings.
Innovation Solution
A multi-layer mask approach is used, comprising a titanium-containing mask layer over a tungsten-containing mask layer, which provides high etching selectivity and reduces distortion of interconnect openings, thereby improving the accuracy and efficiency of the dual damascene process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single-layer mask is used in the dual damascene process, then the process is simpler and faster, but etching selectivity is insufficient and distortion of interconnect openings occurs
Solution Approach 1:
The mask structure is segmented into multiple layers: a first mask layer (e.g., silicon oxide) and a second mask layer (e.g., tungsten carbide) deposited sequentially. Each layer provides different etching selectivity characteristics, allowing precise control over the etching process for forming both the trench and via openings while preventing distortion of the interconnect openings.
Solution Approach 2:
The mask structure uses composite materials with different etching selectivity properties. The first mask layer material (e.g., silicon oxide) and second mask layer material (e.g., tungsten carbide) are selected to provide complementary etching characteristics, enabling high selectivity for different etching steps in the dual damascene process.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases and costs decrease, but challenges in forming accurate interconnect openings arise
Solution Approach 1:
The multi-layer mask structure is prepared in advance with specific thicknesses and material compositions before the etching process. The first and second mask layers are deposited with controlled thicknesses (e.g., 50-200 nm and 20-100 nm respectively) to pre-establish the selective etching conditions needed for accurate interconnect opening formation at scaled dimensions.
Solution Approach 2:
The mask layer parameters (material composition, thickness, deposition conditions) are optimized to provide the required etching selectivity at scaled geometries. By adjusting these parameters, the mask structure maintains its effectiveness for forming precise interconnect openings even as device dimensions decrease.
Data Source
AI summary
A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.