Dual Damascene Interconnection Structure for Low RC Delay
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Solution Overview
Problem
Conventional interconnection structures in integrated circuits face high parasitic capacitance and leakage currents due to small line spacing, leading to increased RC delay and power consumption, with existing methods to reduce dielectric constant being limited and compromising mechanical properties.
Innovation Solution
A novel interconnection structure featuring a dual damascene design with conductive lines and vias, where the width of the overlying metal line is between 65% to 95% of the via width, and the spacing between parallel lines is increased, reducing parasitic capacitance without altering the pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If line spacing is reduced to decrease pitch, then device density is improved, but parasitic capacitance increases leading to higher RC delay
Solution Approach 1:
The patent applies different line width ratios at different locations: lines adjacent to vias have width between 0.5P-0.6P, while lines not adjacent to vias have width between 0.3P-0.4P. This local differentiation reduces parasitic capacitance in critical areas without compromising overall device density.
Solution Approach 2:
The patent introduces dynamic line width adjustment based on positional context. The line width is not fixed but varies depending on whether the line is adjacent to a via or not, allowing optimization of RC delay while maintaining density.
2Productivity
If line spacing is reduced to increase density, then more interconnections fit in given area, but leakage current increases
Solution Approach 1:
The patent implements local quality by assigning different line widths to lines based on their proximity to vias. Lines adjacent to vias maintain larger width (0.5P-0.6P) to control leakage, while other lines use smaller width (0.3P-0.4P) to maximize density.
3Loss of time
If dielectric constant is reduced to decrease parasitic capacitance, then RC delay is improved, but mechanical strength decreases
Solution Approach 1:
Instead of changing the dielectric constant parameter, the patent changes the geometric parameters (line widths) to control parasitic capacitance. This avoids the mechanical strength issues associated with low-k materials while still achieving RC delay improvement.
Data Source
AI summary
An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric layer. The dual damascene structure includes a second conductive line and a via between and adjoining the first and the second conductive lines, wherein the second conductive line comprises a first portion directly over and adjoining the via, and a second portion having no underlying and adjoining vias. The second portion has a second width less than a first width of the first portion.