Dual Damascene Interconnection Patterning via Multi-Mask Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing dual damascene process struggles to form fine interconnection structures due to inaccuracies in patterning and etching with hard masks, leading to unreliable interconnection isolation spacing and reduced reliability of semiconductor device interconnections.
Innovation Solution
A method involving multiple mask films and etching processes to form interconnection patterns and via patterns simultaneously with high accuracy, using first and second mask films to selectively etch films, allowing for precise formation of dual damascene structures with fine interconnection features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a hard mask with interconnection pattern is formed and removed in the conventional dual damascene process, then the process can be completed, but accurate patterning and etching cannot be realized, leading to inability to form fine interconnection structure
Solution Approach 1:
The patent divides the masking function into multiple separate mask films (first mask film, second mask film, third mask film) instead of using a single hard mask. Each mask film is formed at different stages and serves specific purposes: the first mask film defines via patterns, the second mask film defines interconnection patterns, and the third mask film provides protection. This segmentation allows each mask to be optimized for its specific function, achieving fine patterning accuracy while managing process complexity through systematic organization.
Solution Approach 2:
The patent forms the first mask film with via patterns before forming the second mask film with interconnection patterns. This preliminary action allows the via holes to be etched first, creating a foundation for subsequent interconnection trench formation. The mask films are formed in advance with precise patterns before the actual etching occurs, ensuring that fine interconnection structures can be accurately defined before the etching process begins.
2Reliability
If conventional dual damascene process is used, then interconnection trench and via hole are formed, but interconnection isolation spacing is unreliable, reducing semiconductor device reliability
Solution Approach 1:
The patent introduces a third mask film as an intermediary protective layer formed after the second mask film. This third mask film serves as a mediator that protects the previously formed interconnection patterns and via patterns during subsequent etching processes. By having this intermediary protection layer, the isolation spacing between interconnections is maintained more reliably, preventing accidental damage or deformation that would compromise device reliability while preserving the precision of the formed structures.
3Manufacturing precision
If multiple mask films are used to form fine interconnection structure, then patterning accuracy is improved, but process steps increase
Solution Approach 1:
The patent merges multiple patterning functions into a coordinated sequence of mask film formations and etching steps. Instead of treating each mask formation as a separate, isolated process, the method integrates them into a unified flow where the first, second, and third mask films work together in a systematic sequence. This merging allows the complex multi-mask process to be executed more efficiently, improving interconnection pattern accuracy while minimizing the negative impact on manufacturing efficiency through optimized process integration.
Data Source
AI summary
In a dual damascene process to form a fine interconnection structure, a semiconductor manufacturing method includes: forming a first film to be etched on an insulating layer on a semiconductor substrate; forming a first mask film with an opening on the first film; forming a second film to be etched on the first mask film, burying the opening; forming a second mask film on the second film to be etched; forming an interconnection pattern in the second mask film in the upper portion of the opening; forming an interconnection pattern by etching the second film using the second mask film, forming a via pattern by etching the first film to be etched using the first mask film; and forming a via hole and an interconnection trench in the upper portion of the via hole in the insulating layer by selectively etching the insulating layer using the interconnection and via patterns.