Dual Damascene Interconnect Mask Stack for CD Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is producing interconnect structures with a sufficient critical dimension (CD) difference between the top of a conductive trench and the bottom of a conductive via, as existing etching processes struggle to maintain adequate mask layer protection and achieve the required CD differences for advanced technology nodes.
Innovation Solution
A novel etching process involving a mask stack with a first and second mask layer, where the second mask layer is protected by the first mask layer during a trim process, allowing for expanded openings in the semiconductor structure without reducing the mask layer thickness, enabling a sufficient CD difference between the trench and via openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a trim process is applied to expand the opening in the mask layer to obtain a desired top CD value, then the top CD is improved, but the thickness of the mask layer is reduced which results in insufficient protection during the subsequent etching process
Solution Approach 1:
The mask layer is divided into multiple segments (first mask layer and second mask layer) stacked vertically. The first mask layer undergoes the trim process to achieve the desired top CD, while the second mask layer remains intact to provide protection during etching. This segmentation allows independent optimization of each layer's function.
Solution Approach 2:
The solution transitions from a single-layer mask to a multi-layer mask structure in the vertical dimension. By adding the second mask layer beneath the first mask layer, the system gains an additional degree of freedom to simultaneously achieve lateral expansion (via trim on first layer) and vertical protection (via second layer).
2Reliability
If the mask layer thickness is maintained to provide sufficient protection during etching, then the mask layer protection is improved, but the ability to expand the opening laterally to achieve sufficient CD difference is limited
Solution Approach 1:
The mask structure is segmented into a first mask layer for lateral expansion and a second mask layer for thickness maintenance. This allows the second mask layer to preserve full thickness for protection while the first mask layer provides the necessary lateral opening expansion through the trim process.
Solution Approach 2:
The solution uses the vertical dimension to resolve the lateral expansion limitation. By stacking mask layers vertically, the system can expand openings laterally in the first layer without compromising the thickness of the second layer, thereby achieving sufficient CD difference while maintaining protection.
3Device complexity
If a single mask layer is used to form both the trench opening and via opening, then the device complexity is reduced, but the manufacturing precision of CD difference between trench and via is insufficient
Solution Approach 1:
The single mask layer is segmented into two distinct mask layers with different functions. The first mask layer is optimized for forming the trench opening with expanded dimensions, while the second mask layer is optimized for forming the via opening with precise dimensions, enabling sufficient CD difference.
Solution Approach 2:
Different regions of the mask structure are assigned different qualities: the first mask layer has properties optimized for lateral expansion and trench formation, while the second mask layer has properties optimized for thickness maintenance and via formation, allowing precise control of CD difference.
Data Source
AI summary
A method for fabricating a semiconductor device that includes forming a mask stack over a semiconductor structure. The mask stack has a first mask layer and a second mask layer, where the second mask layer is arranged between the first mask layer and the semiconductor structure. The method further includes patterning a first pattern in the mask stack. The first pattern includes a first opening having first sidewalls formed in the first mask layer, a second opening having second sidewalls formed in the second mask layer, and a third opening having third sidewalls formed in the semiconductor structure. The first, second, and third sidewalls of the respective openings of the first pattern are formed around a central axis, where the second sidewalls of the second opening are located further away from the central axis than both the first and third sidewalls of the first and third openings, respectively.