Dual Damascene Via Etching Depth Control
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Solution Overview
Problem
In semiconductor manufacturing, copper interconnects pose challenges due to incompatibility with conventional aluminum processes, leading to incomplete etching of vias in dielectric layers, resulting in failed metal interconnect structures and poor electric connections.
Innovation Solution
A method for forming a dual damascene structure that considers a periodic parameter to ensure thorough removal of interlayer dielectric materials during etching, using a substrate with an etching stop layer and interlayer dielectric layer, where the photo resist layer thickness is determined to achieve correct etching depth, facilitated by a light source with specific periodic parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithographic and etching steps are used to form vias in the interlayer dielectric layer, then the manufacturing process is simple and familiar, but the vias may not thoroughly remove all interlayer dielectric materials, resulting in poor electric connections
Solution Approach 1:
The patent applies preliminary action by calculating and determining the photo resist layer thickness before the etching process using the formula (A+B)/C≈X/2. This pre-calculation ensures that the etching depth will be precise and thorough, removing all interlayer dielectric materials from the vias. By determining the correct photo resist thickness in advance, the patent prevents incomplete etching and ensures reliable electric connections without requiring complex real-time adjustments during manufacturing.
2Manufacturing precision
If the photo resist layer thickness is not accurately controlled, then the manufacturing process is easier, but the etching depth becomes incorrect, leading to incomplete via formation
Solution Approach 1:
The patent replaces complex mechanical measurement and control systems with a mathematical calculation approach. Instead of using sophisticated equipment to measure and control photo resist thickness in real-time, the patent uses the formula (A+B)/C≈X/2 to calculate the required thickness based on known parameters (interlayer dielectric layer thickness A, light source periodic parameter C). This substitution of calculation for complex measurement equipment simplifies the manufacturing process while achieving high precision.
3Reliability
If copper is used to replace aluminum for interconnect formation, then the electrical resistance is lower and thermal conductivity is better, but the copper process is highly incompatible with conventional aluminum processes
Solution Approach 1:
The patent applies parameter changes by introducing a specific mathematical relationship (A+B)/C≈X/2 that connects the interlayer dielectric layer thickness, photo resist layer thickness, and light source periodic parameter. This parameter change creates a precise control mechanism for the dual damascene process, enabling copper interconnect formation with reliable via formation. The patent adapts the conventional lithographic process to copper manufacturing by establishing this new parameter relationship, making the process compatible with copper's specific requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures effective metal interconnect structures are formed, ensuring reliable electric connections between semiconductor elements by accurately determining the photo resist layer thickness and etching depth, overcoming the limitations of conventional methods.
Implementation Method 1
the photo resist layer is patterned by a light source to construct a patterned photo resist layer. The light source has a periodic parameter C so that (A+B)/C≈X/2
Implementation Method 2
the interlayer dielectric layer is again patterned by the patterned photo resist layer to construct a second opening on the first opening
Data Source
AI summary
A method for forming a dual damascene structure is disclosed. First a substrate is provided. There are an etching stop layer and an interlayer dielectric layer disposed on the substrate in order. The interlayer dielectric layer has a thickness A. Second, the interlayer dielectric layer is patterned to form a first opening. Later, a photo resist layer with a thickness B is formed on the interlayer dielectric layer. Then, the photo resist layer is patterned by a light source to construct a patterned photo resist layer. Later, the interlayer dielectric layer is again patterned by the patterned photo resist to pattern the interlayer dielectric layer to construct a second opening on the first opening by means of a light source and the photo resist layer so as to form a dual damascene structure. The light source has a periodic parameter C so that (A+B)/C≈X/2, where X is an odd number.