Dual Damascene Wiring Adhesion and Capacitance Trade-off
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Solution Overview
Problem
Current semiconductor devices with dual damascene multilayer wiring structures face challenges in reducing capacitance between narrow wiring widths and preventing layer separation in wide wiring widths, leading to reduced yield and increased susceptibility to electro and stress migration.
Innovation Solution
The implementation of a semiconductor device with a dual damascene structure that distinguishes between layers requiring an adhesive layer and those that do not, based on aspect ratios, where an adhesive layer with high film strength is used in power wiring layers to enhance adhesion and prevent separation, and no adhesive layer is used in local wiring layers to reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a stopper layer is formed in the local wiring layer, then the adhesion between layers is improved, but the capacitance between wirings increases
Solution Approach 1:
The invention applies different structural configurations to different wiring layers based on their specific requirements. The local wiring layer (with narrow pitch) omits the stopper layer to minimize capacitance, while the power wiring layer (with wide pitch) includes the stopper layer to ensure adhesion and prevent layer separation. This localized differentiation resolves the contradiction by optimizing each layer's structure according to its functional needs.
2Object-affected harmful factors
If no stopper layer is formed (stopper-less structure), then the capacitance between wirings is reduced, but layer separation occurs easily in assembling processes
Solution Approach 1:
The invention implements a selective stopper layer strategy where the presence or absence of the stopper layer is determined by the specific wiring layer's characteristics. Narrow-pitch layers use the stopper-less structure to minimize capacitance, while wide-pitch layers incorporate the stopper layer to prevent layer separation during assembly, thus resolving the contradiction through localized structural optimization.
3Speed
If the wiring pitch is narrowed to reduce capacitance, then the clock operation frequency is improved, but the yield is lowered due to layer separation
Solution Approach 1:
The invention allows narrow wiring pitch in local wiring layers to achieve low capacitance and high clock frequency, while simultaneously incorporating stopper layers in power wiring layers to prevent layer separation and maintain high yield. This localized differentiation enables both performance optimization and manufacturing reliability.
4Reliability
If a stopper layer is formed in the power wiring layer, then layer separation is prevented, but the capacitance between wirings increases
Solution Approach 1:
The invention recognizes that power wiring layers have wide pitch and are therefore less sensitive to capacitance effects. Consequently, stopper layers are incorporated in these layers to prevent layer separation, while the resulting capacitance increase is acceptable given the wider spacing between conductors. This localized approach optimizes each layer independently.
Data Source
AI summary
The semiconductor device includes multilayer wirings of a dual damascene structure. The multilayer wirings include a first wiring layer formed on a semiconductor substrate and a second wiring layer formed on the first wiring layer. The first wiring layer includes a first insulation film, plural first vias provided in the first insulation film, a second insulation film provided on the first insulation film, and a first wiring provided on the first vias and connected to those first vias in the second insulation film. The second wiring layer includes a third insulation film, plural second vias provided in the third insulation film, an adhesive layer provided on the third insulation film, a fourth insulation film provided on the adhesive layer, and a second wiring provided on the second vias and connected to those second vias in the fourth insulation film. In the first wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V are in a relationship of L≧V and in the second wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V is in a relationship of L<V.