Dual-Damascene Zero-Misalignment Vias for High I/O Density Packaging
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Solution Overview
Problem
Current semiconductor packaging technologies, such as laser drilling, limit I/O density due to large via pad sizes caused by misalignment and minimum feature size constraints, making it difficult to achieve I/O densities greater than 50 IO/mm/layer.
Innovation Solution
The implementation of a dual-damascene zero-misalignment via process, which uses stacked resist layers or photoimageable dielectric materials, allows for simultaneous plating of vias and traces without misalignment, reducing pad sizes and increasing I/O density by eliminating the need for alignment between vias and traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling processes are used to create via openings, then via openings can be formed through dielectric layers, but the minimum feature size and misalignment of the laser limit the reduction of via pad sizes
Solution Approach 1:
The patent replaces the mechanical laser drilling process with a chemical etching process. Instead of using laser energy to physically drill through dielectric layers, the invention uses chemically selective etching of sacrificial mandrel materials (such as silicon dioxide, silicon nitride, or silicon oxynitride) to form via openings. This substitution eliminates laser misalignment issues and minimum feature size constraints, enabling precise via formation with smaller pad sizes.
Solution Approach 2:
The patent introduces sacrificial mandrel structures as intermediary elements in the via formation process. These mandrels are deposited as placeholder structures that define the via locations and dimensions. The mandrels are then selectively removed through chemical etching, leaving precisely defined via openings. This intermediary approach allows for accurate via placement without relying on laser alignment, directly addressing the misalignment problem.
2Productivity
If via pad sizes are reduced to increase I/O density, then more I/O connections can be achieved per layer, but alignment margins require larger pads beneath vias
Solution Approach 1:
The patent replaces the laser-based mechanical drilling system with a chemical etching system that uses pre-formed sacrificial mandrels. The mandrels are deposited with precise dimensions and locations using standard thin-film deposition techniques, eliminating the need for laser alignment margins. This substitution enables via pads to be reduced to the actual via opening size without requiring additional alignment margins, thereby increasing I/O density.
Solution Approach 2:
The patent performs preliminary action by forming sacrificial mandrel structures before via opening creation. These mandrels are deposited, patterned, and cured in advance to define the exact via locations and dimensions. This preliminary structuring eliminates the need for subsequent alignment operations, as the mandrels themselves serve as the precise templates for via formation, allowing minimal pad sizes.
3Manufacturing precision
If UV lasers are used to reduce via opening size, then smaller vias can be created, but throughput is greatly decreased
Solution Approach 1:
The patent replaces the UV laser drilling system with a chemical etching process. Instead of using high-energy UV photons to ablate material, the invention employs chemical solutions that selectively etch sacrificial mandrel materials. This chemical approach is significantly faster and more scalable than UV laser drilling, maintaining via opening precision while dramatically improving throughput and manufacturing efficiency.
Solution Approach 2:
The patent changes the fundamental parameter of via formation from mechanical/thermal energy removal (laser) to chemical reaction-based material removal (etching). By changing the etching chemistry to be highly selective for the sacrificial mandrel material, the process achieves both small via dimensions and high throughput, as chemical etching can be performed in parallel across large substrate areas without the sequential scanning limitation of laser systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and development time while increasing I/O and trace density by enabling the fabrication of smaller pads and vias, thereby enhancing the input/output connections in semiconductor packages.
Implementation Method 1
The ZMV process method utilizes a photoresist layer with sensitivity to two different light wavelengths, two different light intensities, two different regions of gray-scale photomask, or a combination thereof. In this way, the photoresist layer can be differentially patterned in conjunction with a dose sensitive resist layer.
Implementation Method 2
the vias and traces to be plated in a two-step process without removal of the photoresist layer
Data Source
AI summary
Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.