Dual Data Connection Architecture for Mixed Latency and Bandwidth
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Solution Overview
Problem
Current data processing devices face challenges in meeting simultaneous requirements of low latency and high data rates due to the contradictory nature of latency and data-rate optimization, which limits their performance in real-time applications.
Innovation Solution
A data processing device with a dual data connection architecture, where one connection is optimized for high data rates and another for low latency, allowing the same system to handle both high data-rate and low-latency applications by using a crossbar architecture and separate data connections for processor-to-accelerator and processor-to-peripheral communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single data connection is used for both processor-to-accelerator and processor-to-peripheral communication, then device complexity is reduced, but it becomes impossible to simultaneously meet low latency and high data rate requirements
Solution Approach 1:
The patent divides the data connection architecture into two separate connections: a first data connection optimized for high data rates (processor-to-accelerator) and a second data connection optimized for low latency (processor-to-peripheral). This segmentation allows each connection to be independently optimized for its specific application requirements without compromising the other.
Solution Approach 2:
The patent introduces an additional dimension to the data connection architecture by adding a second separate data connection. Instead of trying to optimize a single connection for conflicting requirements, the solution moves to a multi-dimensional architecture where different connections operate in parallel with different optimization characteristics.
2Productivity
If data connections are optimized for high data rates, then data throughput increases, but latency increases making low-latency applications impossible
Solution Approach 1:
The patent segments the data transmission paths into two distinct connections with different optimization characteristics. The first connection prioritizes data rate for bulk data transfer to the accelerator, while the second connection prioritizes low latency for time-critical peripheral communications, allowing both performance metrics to be achieved simultaneously for their respective applications.
Data Source
AI summary
A data processing device is provided. The data processing device includes at least one processor circuit, at least one additional circuit, an accelerator circuit, a first data connection which at least connects the at least one processor circuit to the accelerator circuit and is configured to exchange data between the at least one processor circuit and the accelerator circuit, a second data connection which connects the at least one processor circuit to the at least one additional circuit and is configured to exchange data between the at least one additional circuit and the processor circuit, wherein the first data connection has a higher data rate or a lower latency than the second data connection, and includes an address segment having a first address range, which has at least one first address each for the at least one additional circuit and the accelerator circuit, and a second address range which has at least one second address each for the at least one additional circuit and the accelerator circuit, wherein the data processing device is configured to exchange data using the first data connection when addressing using one of the first addresses, and to exchange data using the second data connection when addressing using one of the second addresses.