Display Substrate Layout for Dual Data Lines and High-Resolution Driving
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Solution Overview
Problem
Existing OLED display substrates with dual data lines face challenges in achieving high resolution due to limitations in design, which impedes their ability to meet market demands.
Innovation Solution
The display substrate incorporates a novel layout with power lines connected through functional layers, featuring sub-power lines with specific angular arrangements and overlapping areas, along with a detailed structure of transistors and capacitors to enhance connectivity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual data lines are used for high-frequency driving, then driving frequency is improved, but resolution deteriorates
Solution Approach 1:
The data transmission function is segmented into two separate data lines (first data line and second data line), allowing independent control and timing. This segmentation enables the pixel array to be divided into different regions (first pixel array and second pixel array) that can be driven at different frequencies, thus achieving high-frequency driving while maintaining high resolution across the entire display.
Solution Approach 2:
The patent introduces a temporal dimension by implementing different scanning frequencies for different data lines and pixel regions. The first data line operates at a first scanning frequency while the second data line operates at a second scanning frequency, creating a multi-frequency driving scheme that resolves the contradiction between driving frequency and resolution.
2Ease of manufacture
If power lines are arranged in traditional layouts, then manufacturing is simplified, but power distribution efficiency deteriorates
Solution Approach 1:
The power line layout is optimized with local quality by creating different power distribution paths for different regions. The first power line is arranged in a first region while the second power line is arranged in a second region, allowing each region to receive power through optimized local paths that reduce resistance and improve power distribution efficiency without complicating the overall manufacturing process.
3Use of energy by moving object
If sub-power lines are arranged with specific angular orientations, then power distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The sub-power lines are arranged with asymmetric angular orientations relative to the gate lines. The first sub-power line forms a first angle with the gate lines while the second sub-power line forms a second angle, creating an asymmetric layout that optimizes power distribution paths for different pixel regions. This asymmetric arrangement improves power distribution efficiency by reducing interference and optimizing current flow paths.
Solution Approach 2:
The patent utilizes angular orientation as an additional spatial dimension for power line arrangement. By varying the angles of sub-power lines relative to gate lines, the design creates three-dimensional routing optimization on a two-dimensional plane, improving power distribution efficiency without significantly increasing manufacturing complexity.
Data Source
AI summary
Disclosed are a display substrate and a manufacturing method thereof, and a display apparatus. The display substrate includes, in a plane parallel to the display substrate, a plurality of gate lines, a plurality of data lines, a plurality of power lines and a plurality of sub-pixels arranged on a base substrate. At least one sub-pixel includes a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light. The driving circuit includes a plurality of transistors and a storage capacitor. The display substrate includes, in a plane perpendicular to the display substrate, a base substrate and a plurality of functional layers. The plurality of functional layers includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially arranged.