Dual-Decimator Signal Measurement for Waveform and Bus Decode Analysis
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Solution Overview
Problem
Existing measurement systems provide limited insights by separately analyzing analog and digital signals in electronic circuits, particularly when acquiring waveforms from digital bus systems, as they only decode digital data without detailed waveform analysis.
Innovation Solution
A measurement application device with dual decimators and decoders that process analog input signals to provide both decimated digital input signals and decoded digital signals, allowing concurrent analysis of waveforms and data content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single decimator is used to process digital input signals, then the device complexity is reduced, but the measurement precision and analysis capability are limited because only one type of processed signal can be provided
Solution Approach 1:
The patent divides the signal processing function into two separate decimators: a first decimator that reduces samples by a first factor and a second decimator that reduces samples by a second factor. This segmentation allows the system to provide multiple types of processed signals simultaneously, improving measurement precision without requiring a single complex processing unit.
Solution Approach 2:
The patent adds a dimension of processing diversity by implementing decimators with different reduction factors. Instead of simply increasing the complexity of a single decimator, the system creates parallel processing paths with different characteristics, enabling simultaneous provision of coarsely and finely decimated signals for comprehensive analysis.
2Measurement precision
If high-resolution waveform analysis is performed on digital bus systems, then the measurement precision is improved, but the loss of time increases because detailed sampling requires more processing time
Solution Approach 1:
The patent applies partial action by providing two levels of decimation: coarse decimation for quick overview and fine decimation for detailed analysis. This allows the system to process signals at different resolutions simultaneously, enabling users to quickly assess overall waveform characteristics while having the option to examine specific details without processing the entire high-resolution signal.
Solution Approach 2:
The patent changes the sampling parameter by implementing variable decimation factors. The first decimator uses a first reduction factor while the second decimator uses a second reduction factor, allowing the system to adapt the processing resolution to different analysis needs and reduce overall processing time by handling coarse analysis separately from fine analysis.
3Adaptability or versatility
If multiple decimators with different reduction factors are implemented, then the adaptability of the measurement device is improved, but the device complexity increases due to additional processing components
Solution Approach 1:
The patent implements universality by designing a measurement application device that can simultaneously provide multiple types of processed signals (coarsely decimated and finely decimated) through a unified architecture. The multiple decimators and decoders work together in a coordinated manner, allowing the device to adapt to different analysis requirements without requiring separate independent systems.
Solution Approach 2:
The patent applies the nesting principle by organizing the decimators and decoders in a hierarchical structure where the first decimator and second decimator process the same digital input signal in parallel, and their outputs are further processed by respective decoders. This nested arrangement allows efficient resource utilization and coordinated operation of multiple processing components.
Data Source
AI summary
The present disclosure provides a measurement application device comprising at least one signal acquisition interface configured to acquire an analog input signal and output a digital input signal, a first decimator for each signal acquisition interface, each one of the first decimators being configured to reduce the number of samples of the respective digital input signal and output a first decimated digital input signal, at least one second decimator for each signal acquisition interface, each one of the second decimators being configured to reduce the number of samples of the respective digital input signal and output a second decimated digital input signal, and at least one decoder for each one of the second decimators, each one of the decoders being configured to decode the respective second decimated digital input signal according to a respective protocol and provide a respective decoded input signal.