Dual-Deck Channel Hole Structure for 3D Memory
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Solution Overview
Problem
As semiconductor technology advances, 3D memory devices face challenges in etching processes due to the scaling of oxide/nitride layers, making it difficult to form channel holes effectively, which limits memory density and increases fabrication costs.
Innovation Solution
A method for forming a dual-deck channel hole structure in 3D memory devices involves creating a first and second alternating dielectric stack, forming channel holes, and inserting a sacrificial inter-deck plug, which is then replaced with an inter-deck channel plug to enhance channel mobility and string current, while maintaining a robust structure with limited thickness and enlarged dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single-deck channel hole formation process is used, then fabrication process is simpler, but memory density is limited and etching becomes challenging as oxide/nitride layers scale
Solution Approach 1:
The patent divides the channel hole formation into two separate decks: a first deck with first channel holes formed through the first alternating dielectric stack, and a second deck with second channel holes formed through the second alternating dielectric stack. This segmentation allows each deck to be optimized independently for etching processes, enabling better control as oxide/nitride layers scale while achieving higher memory density through the dual-deck structure.
2Productivity
If oxide/nitride layers are scaled to increase memory density, then memory density improves, but etching process becomes more challenging
Solution Approach 1:
By segmenting the structure into two separate alternating dielectric stacks (first and second stacks with different material compositions), the patent enables independent optimization of etching parameters for each deck. The first stack uses oxide/nitride layers optimized for first channel hole etching, while the second stack uses different oxide/nitride layer configurations optimized for second channel hole etching, maintaining manufacturing precision despite scaled dimensions.
Solution Approach 2:
The patent applies local quality by using different oxide/nitride layer compositions and thicknesses in different regions: the first alternating dielectric stack has specific oxide/nitride layer configurations optimized for first channel holes, while the second alternating dielectric stack has different configurations optimized for second channel holes. This localized optimization enables precise control of etching processes in each region despite overall scaling.
3Productivity
If dual-deck structure is formed to increase memory density, then memory density improves, but fabrication cost increases
Solution Approach 1:
The patent segments the fabrication into two decks that can be processed in parallel or sequentially using similar process steps. By forming first and second alternating dielectric stacks with different oxide/nitride layer configurations, the patent enables reuse of comparable fabrication equipment and processes for both decks, reducing the incremental cost of achieving higher density compared to a single complex optimized process.
4Productivity
If channel hole etching is performed on scaled oxide/nitride layers, then memory density increases, but etching process control becomes difficult
Solution Approach 1:
The patent improves etching reliability by segmenting the structure into two decks with different oxide/nitride layer configurations. Each deck can be etched with optimized parameters specific to its layer composition, ensuring consistent and reliable etching results even as overall dimensions are scaled down to increase memory density.
Solution Approach 2:
By providing locally optimized oxide/nitride layer configurations in each deck (first stack with specific layer structures for first channel holes, second stack with different layer structures for second channel holes), the patent ensures that etching processes remain reliable and controllable in each region, preventing the reliability degradation that would occur with uniform scaled structures.
Data Source
AI summary
A method for forming a channel hole structure of a 3D memory device is disclosed. The method includes: forming a first alternating dielectric stack and a first insulating layer on a substrate; forming a first channel structure in a first channel hole penetrating the first insulating layer and the first alternating dielectric stack; forming a sacrificial inter-deck plug in the first insulating layer; forming a second alternating dielectric stack on the sacrificial inter-deck plug; forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug; removing the sacrificial inter-deck plug to form a cavity; and forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, the inter-deck channel plug contacts the first channel structure and the second channel structure.