Dual-Decoder LDPC Architecture for NAND Flash Latency Reduction

The patent implements dynamic iteration termination by monitoring syndrome weight during the iterative decoding process. The decoder adaptively stops iterations when the syndrome weight indicates sufficient error correction, rather than executing a fixed number of iterations. This dynamic approach allows the system to maintain high error correction capability while significantly reducing latency when errors are few or already corrected, thereby resolving the contradiction between reliability and time loss.

The patent changes the decoding parameter (number of iterations) based on the syndrome weight threshold. When syndrome weight falls below the threshold, iterations are terminated early; otherwise, full iterations continue. This parameter adjustment strategy maintains error correction effectiveness while optimizing decoding speed, effectively balancing reliability and latency requirements.

The patent applies partial action by performing only the necessary number of decoding iterations required to achieve error correction, rather than always executing the maximum number of iterations. The syndrome weight threshold mechanism allows the system to stop iterations early when error correction is sufficient, reducing computational burden and processing complexity while maintaining effective error correction when needed.

The patent implements feedback control by continuously monitoring the syndrome weight during iterative decoding and using this information to determine whether to continue or terminate iterations. This feedback mechanism ensures that processing resources are allocated efficiently - full iterations are performed only when necessary, thereby reducing overall processing burden while maintaining error correction effectiveness.

The patent replaces the mechanical approach of fixed iterative decoding with a syndrome-weight-based termination mechanism. Instead of blindly executing a predetermined number of iterations, the system uses the syndrome weight (a mathematical indicator of error presence) to intelligently determine when to stop. This substitution ensures that early termination does not compromise error correction capability, as iterations continue until the syndrome weight confirms sufficient correction, thereby maintaining reliability while reducing latency.

The patent performs preliminary assessment of error correction status by calculating and monitoring syndrome weight at each iteration. This preliminary action allows the system to predict whether additional iterations are necessary before committing computational resources, enabling early termination when errors are already corrected while ensuring continued iterations when errors persist, thus balancing latency reduction with error correction capability.