Dual Delay Circuit Calibration for Accurate Clock Skew Detection
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Solution Overview
Problem
Current clock skew detection techniques in synchronous circuits lack accuracy, leading to ineffective correction and inefficient resource utilization due to rough deviation measurement limitations.
Innovation Solution
A delay difference detection and adjustment device comprising a first delay circuit, a second adjustable delay circuit, a storage circuit, a delay control circuit, and an analyzing circuit, which detects and adjusts the delay difference between the two circuits to enhance clock detection precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current clock skew detection techniques are used, then the detection process is simple, but the measurement precision is insufficient due to element precision limitations
Solution Approach 1:
The detection device is segmented into multiple functional modules: first delay circuit with first delay units, second delay circuit with second delay units, storage circuit with storage units, delay control circuit, and analyzing circuit. Each module performs a specific function in the delay difference measurement process, allowing for precise measurement while maintaining clear functional separation.
Solution Approach 2:
The storage circuit acts as an intermediary between the two delay circuits and the analyzing circuit. It stores the first clock signals at different time points determined by the second clock, enabling the analyzing circuit to accurately measure delay differences without direct complex interaction between the delay circuits.
2Reliability
If guard bands or clock de-rating factors are added to enhance tolerance to clock skew, then the circuit becomes more robust, but design resources are wasted due to loose design requirements
Solution Approach 1:
The device provides accurate feedback on the actual clock skew magnitude through the analyzing circuit, which calculates delay differences based on stored clock signals. This feedback mechanism enables precise calibration without requiring excessive guard bands or de-rating factors, optimizing the balance between reliability and resource efficiency.
Solution Approach 2:
The delay control circuit adjusts the delay amount of the second delay circuit dynamically to match the first delay circuit. By changing the delay parameter precisely based on measured skew, the system achieves optimal synchronization without requiring fixed conservative margins.
3Measurement precision
If the minimal delay amount of delay elements is used, then the device complexity is low, but the measurement precision of clock deviation is insufficient
Solution Approach 1:
The invention measures delay difference not by using a single large delay element but by comparing multiple smaller delay units across two different delay circuits. This dimensional approach - using multiple units in series and parallel configurations - achieves fine-grained measurement precision without requiring excessively complex individual elements.
Solution Approach 2:
The device uses multiple delay units (first and second delay units) where the combined delay exceeds what a single minimal element would provide. By using partial delays from multiple units and comparing them, the system achieves precise measurement capability beyond what a single element could deliver.
Data Source
AI summary
The present invention discloses a delay difference detection and adjustment device comprising: a first delay circuit including first delay units to receive and transmit a first clock; a second delay circuit including second delay units to receive and transmit a second clock; a storage circuit including storage units, each of which includes a data input end to receive the first clock and an operation clock reception end to receive the second clock, so that the storage circuit is operable to save a plurality of levels of the first clock according to the second clock; a delay control circuit to adjust the delay amount of the second delay circuit; and an analyzing circuit to generate an analysis result according to the cycle and levels of the first clock in which the analysis result indicates or is used to derive a unit delay difference between the first and second delay units.