Dual-Delay DLL Circuit for Low-Power Jitter-Robust Clock Locking
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Solution Overview
Problem
Conventional DLL circuits face challenges in reducing power consumption while maintaining high-speed operation, as they either consume less power but increase signal loading and jitter, or consume more power to combat jitter but are limited by complex signal relationships and sensitivity to PVT variables.
Innovation Solution
A DLL circuit that uses different types of delay cells for coarse and fine locking, with a first delay line comprising differential amplifiers and a second delay line comprising inverters, along with a phase detection and control unit to manage delay times and a replica delay path for compensation, effectively reducing power consumption and robustly handling PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL circuits use delay cells to perform phase adjustment, then signal synchronization is achieved, but power consumption increases and jitter is introduced
Solution Approach 1:
The delay line is segmented into multiple delay cells (first delay cell, second delay cell, third delay cell) that can be independently controlled. This segmentation allows the circuit to achieve phase adjustment with fewer active delay cells, thereby reducing power consumption while maintaining signal synchronization capability.
Solution Approach 2:
The delay cells are dynamically controlled through selection signals (first selection signal, second selection signal) that enable or disable specific delay cells based on the required phase adjustment. This dynamic control allows the circuit to consume minimal power by activating only the necessary delay cells while maintaining the ability to achieve precise phase synchronization.
2Reliability
If delay cells are used to reduce jitter, then signal stability improves, but signal loading increases and circuit complexity increases
Solution Approach 1:
The delay line is divided into multiple independent delay cells with separate control signals. This segmentation allows precise control over which cells are active, reducing the overall circuit complexity compared to a monolithic delay structure while maintaining signal stability through selective activation of delay elements.
Solution Approach 2:
The circuit changes the delay parameter by selectively enabling or disabling specific delay cells based on control signals. This parameter adjustment mechanism allows the circuit to achieve the required signal stability with minimal active components, thereby reducing circuit complexity while maintaining performance.
3Use of energy by moving object
If more delay cells are activated to reduce power consumption, then power efficiency improves, but signal loading and jitter increase
Solution Approach 1:
The delay cells are dynamically controlled through selection signals that enable or disable specific cells based on the required phase adjustment. This dynamic control allows the circuit to consume minimal power by activating only the necessary delay cells while maintaining signal quality through precise control of the active delay path.
Solution Approach 2:
The circuit adjusts the delay parameter by selectively activating delay cells based on control signals. This parameter control mechanism ensures that the minimum necessary number of delay cells are activated to achieve the required phase adjustment, thereby optimizing power consumption while maintaining signal quality through controlled signal propagation.
Data Source
AI summary
A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.