Dual-Delay DLL Handoff for Wide Tuning Range and Low Jitter
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Solution Overview
Problem
Source-synchronous systems face challenges in achieving a wide tuning range for delay-locked loops at high data rates without increasing power consumption, jitter, and phase noise, as conventional delay lines require a wide tuning range that correlates with these issues.
Innovation Solution
A delay-locked loop with two delay lines, where the DLL selects between them based on phase differences, allowing for a handoff between the lines to maintain a relatively wide tuning range while keeping each line's operating range restricted, thereby reducing power consumption and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single delay line is designed to cover a wide tuning range for high data rates, then the tuning range is sufficient, but power consumption increases and jitter and phase noise worsen
Solution Approach 1:
The delay line is divided into multiple segments (first delay line and second delay line), each covering a specific phase difference range. The controller selectively activates only the required segment based on the detected phase difference, thereby achieving wide overall tuning range while minimizing power consumption by keeping individual segments compact and selectively operational.
2Adaptability or versatility
If a single delay line is designed to cover a wide tuning range for high data rates, then the tuning range is sufficient, but jitter and phase noise increase
Solution Approach 1:
The delay line is divided into multiple segments (first delay line and second delay line), each covering a specific phase difference range. The controller selectively activates only the required segment based on the detected phase difference, thereby achieving wide overall tuning range while minimizing power consumption by keeping individual segments compact and selectively operational.
3Use of energy by moving object
If a reduced tuning range is used for the delay line, then power consumption and jitter are reduced, but the tuning range becomes insufficient for high data rates
Solution Approach 1:
The system achieves multi-functionality by implementing multiple delay line segments that can be selectively activated. Each segment serves as a universal building block that can operate independently to cover different phase difference ranges, allowing the system to adapt its effective tuning range dynamically while maintaining low power consumption in each individual segment.
Solution Approach 2:
The system dynamically switches between different delay line segments based on the detected phase difference. The controller monitors the phase difference and selectively enables the appropriate segment (first or second delay line), making the tuning range adaptive and dynamic rather than fixed, thereby achieving wide effective coverage without requiring any single segment to have large inherent range.
4Adaptability or versatility
If a single delay line with wide tuning range is used, then high data rate operation is enabled, but device complexity increases
Solution Approach 1:
The delay line is divided into multiple segments (first delay line and second delay line), each covering a specific phase difference range. The controller selectively activates only the required segment based on the detected phase difference, thereby achieving wide overall tuning range while minimizing power consumption by keeping individual segments compact and selectively operational.
Data Source
AI summary
A delay-locked loop (DLL) is provided that includes both a first delay line and a second delay line. The delay-locked loop functions to synchronize a DLL output clock signal relative to a received clock signal using the first delay line while a phase difference between the received clock signal and a received data signal corresponds to a delay within an operating range for the first delay line. As the phase difference increases to force the first delay line out of its operating range, the delay-locked loop transitions to using the second delay line to synchronize the DLL output clock signal relative to the received clock signal.