Dual Delay-Line Data Input for Continuous Clock Phase Correction
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Solution Overview
Problem
In memory circuits, variations in temperature and voltage cause clock signal phase deviations, leading to increased error rates during data sampling, and existing correction methods often require interrupting data transmission.
Innovation Solution
A data input device employing a first and second delay line, a detection circuit, and a processing circuit to adjust delay magnitudes, allowing for continuous data transmission by selecting between delayed data sets based on deviation detection, ensuring the sampling clock hits the center of each data piece.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single delay line is used to correct clock phase deviation, then data accuracy is improved, but transmission continuity is interrupted
Solution Approach 1:
The patent divides the correction function into two separate delay lines (first delay line and second delay line) instead of using a single delay line. Each delay line handles different correction scenarios, allowing the system to switch between them based on detected deviation directions. This segmentation enables continuous correction without interrupting data transmission.
Solution Approach 2:
The patent dynamically adjusts delay parameters based on detected phase deviation. The detection circuit identifies deviation direction and magnitude, then the processing circuit modifies the delay parameters of appropriate delay lines accordingly. This parameter adjustment occurs continuously without stopping data transmission, maintaining both accuracy and continuity.
2Measurement precision
If delay magnitude is adjusted to correct phase deviation, then sampling accuracy is improved, but system complexity increases
Solution Approach 1:
The correction system is segmented into distinct functional blocks: detection circuit for identifying deviation, processing circuit for decision-making, and two separate delay lines for execution. This segmentation makes the complex function more manageable and easier to implement compared to a monolithic correction mechanism.
Solution Approach 2:
The system performs self-correction through automatic detection and adjustment. The detection circuit continuously monitors phase deviation, and the processing circuit automatically adjusts delay parameters without external intervention. This self-service mechanism reduces the need for complex external control systems.
Data Source
AI summary
A data input device includes a first delay line, a second delay line, a detection circuit, and a processing circuit. The detection circuit is configured to detect whether a first output data output to a system circuit deviates from a first detection range and to generate a first deviation signal in response to that the detection circuit detects the first output data deviates from the first detection range. The processing circuit normally takes a first delayed data delayed by the first delay line as the first output data. In response to that the processing circuit receives that the first deviation signal representing the first delayed data deviates from the first detection range, the processing circuit takes a second delayed data delayed by the second delay line as the first output data after the second adjustable delay magnitude of the second delay line is adjusted.