Dual Delay-Loop Clock Generation for Low-Power Phase Accuracy
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Solution Overview
Problem
Existing clock generation circuits for semiconductor devices require high power consumption to maintain accurate phase and duty ratio, leading to increased power usage and inefficiency, especially when generating multi-phase clock signals with minimal phase skew.
Innovation Solution
A clock generation circuit comprising a clock receiver, a first delay loop circuit with a single-ended CMOS clock delay line, and a second delay loop circuit with a differential current mode logic (CML) clock delay line, which selectively activates the second loop for high performance and phase accuracy, minimizing power consumption by deactivating it during low power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high performance clock generation circuit (phase-locked loop or delay-locked loop) is used to generate multi-phase clock signals with constant phase difference, then the phase accuracy and skew control are improved, but the power consumption increases significantly
Solution Approach 1:
The clock generation circuit is divided into two independent delay loop circuits: a first delay loop circuit for generating a reference clock signal and a second delay loop circuit for generating internal clock signals. Each circuit operates independently with its own delay elements, allowing selective activation based on performance requirements rather than requiring the entire high-performance system to operate continuously.
Solution Approach 2:
The circuit dynamically changes its operational parameters by selectively enabling or disabling the second delay loop circuit based on the required performance level. When high phase accuracy is needed, the second circuit is activated; when lower performance is acceptable, it is deactivated to reduce power consumption, thus adapting the system parameters to match operational requirements.
2Measurement precision
If a delay-locked loop circuit is used to generate multi-phase clock signals, then the phase skew control is improved, but the circuit complexity increases
Solution Approach 1:
The delay-locked loop functionality is segmented into two separate circuits with different complexity levels. The first delay loop circuit has simpler structure for reference clock generation, while the second delay loop circuit provides enhanced phase skew control when needed. This segmentation allows the system to achieve high performance when required without permanently maintaining the complexity of a full high-performance DDLL circuit.
Solution Approach 2:
The circuit complexity is made dynamic rather than static. The second delay loop circuit can be selectively activated or deactivated based on operational requirements, allowing the system to transition between simple and complex operational states. This dynamic configuration enables the circuit to maintain high phase skew control capability when needed while reducing overall complexity during normal operation.
Data Source
AI summary
A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.