Dual Delay Locked Loop for High-Frequency Clock Phase Locking
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Solution Overview
Problem
Existing delay locked loop circuits face challenges in maintaining precise phase synchronization of internal clock signals due to process variations and mismatch in delay lines, particularly at high frequencies, leading to phase skew and difficulty in locking phases between reference and feedback clock signals.
Innovation Solution
A semiconductor apparatus incorporating a dual delay locked loop circuit with both digital and analog delay locked loops, utilizing a frequency detector, phase detector, selection controller, and charge pump to generate delay control voltage, which compares phases of internal and feedback clock signals to adjust delay lines and maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single delay locked loop circuit is used, then the circuit structure is simple, but phase synchronization precision deteriorates at high frequencies due to process variations and delay line mismatch
Solution Approach 1:
The delay locked loop circuit is divided into two independent loops: a analog delay locked loop (ADLL) and a digital delay locked loop (DDLL). Each loop processes clock signals independently through its own delay line and phase detector, allowing the system to handle different frequency ranges and phase adjustment requirements separately, thereby improving overall phase synchronization precision
Solution Approach 2:
The patent introduces a new dimension by operating two delay locked loops simultaneously at different operational dimensions - the ADLL operates in the analog domain for fine phase adjustment while the DDLL operates in the digital domain for coarse phase adjustment. This multi-dimensional approach enables precise phase locking that neither single-loop configuration could achieve alone
2Reliability
If delay lines are adjusted to compensate for phase difference, then phase synchronization is improved, but phase skew increases due to process variations and mismatch
Solution Approach 1:
Each delay line in the dual-loop configuration is designed with locally optimized delay elements that are matched within their respective loops. The analog delay line uses continuously adjustable delay elements while the digital delay line uses discretely adjustable elements, allowing each loop to independently compensate for local process variations and minimize phase skew within its operational range
Solution Approach 2:
The patent employs different delay adjustment parameters for the two loops: the ADLL continuously varies delay parameters to achieve fine phase adjustment, while the DDLL steps through discrete delay values for coarse adjustment. This multi-parameter approach allows the system to adapt to process variations and minimize phase skew across different operating conditions
3Measurement precision
If a dual delay locked loop circuit is used, then phase synchronization precision is improved across broader frequency range, but device complexity increases
Solution Approach 1:
The patent merges the analog and digital delay locked loops into a unified dual-loop system that shares common components such as the reference clock input, feedback path, and control logic. This merging approach allows the two loops to work synergistically, improving phase synchronization precision while minimizing the increase in overall device complexity through resource sharing
Data Source
AI summary
A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.