Dual Delay-Line Multi-Phase Clocking for Duty-Cycle Accuracy
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Solution Overview
Problem
Existing multi-phase clock signal generators fail to produce clock signals with corrected duty-cycles, especially in high-speed systems with wide frequency ranges, and are prone to duty-cycle distortion, which is problematic in applications like memory devices where power supply noise and clock jitter are significant.
Innovation Solution
A multi-phase duty-cycle corrected clock signal generator using a multi-tap adjustable delay line, phase detector, charge-pump and loop filter, and bias generator to synchronize clock signals and correct duty-cycles, ensuring accurate phase relationships and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-tap adjustable delay line is used to generate multi-phase clock signals, then phase relationships can be established, but duty-cycle distortion occurs and cannot be corrected
Solution Approach 1:
The patent segments the clock signal generation into two independent functions: one path (through the adjustable delay line) establishes phase relationships, while another path generates duty-cycle corrected signals. This segmentation allows each path to optimize for its specific function without compromising the other.
Solution Approach 2:
The patent introduces an intermediary duty-cycle correction circuit that takes the multi-phase clock signals from the delay line and generates corrected versions. This intermediary component mediates between the phase-establishing delay line and the final output, eliminating duty-cycle distortion while preserving phase relationships.
2Device complexity
If a fixed timing circuit is used to generate quadrature clock signals, then simple implementation is achieved, but adaptability to wide frequency ranges is lost
Solution Approach 1:
The patent employs an adjustable delay line that can dynamically adapt its delay characteristics based on the input clock frequency. This dynamic adjustment capability allows the circuit to maintain accurate phase relationships across a wide frequency range, unlike fixed timing circuits.
Solution Approach 2:
The adjustable delay line serves multiple functions: it can generate various phase relationships (quadrature, triple-phase, quadruple-phase) and adapt to different frequency ranges. This multi-functionality replaces the need for multiple fixed circuits, achieving versatility without proportionally increasing complexity.
3Device complexity
If multi-phase clock signals are generated without duty-cycle correction, then circuit complexity is reduced, but reliability in high-speed systems deteriorates due to power supply noise and clock jitter
Solution Approach 1:
The patent extracts the duty-cycle correction function as a separate, dedicated circuit component. This extraction allows the correction function to be implemented with specialized circuitry optimized for high-speed operation, improving reliability without burdening the main clock generation path with complex correction logic.
Data Source
AI summary
Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals.