Dual-Density Etch Stop Stack for Low-Capacitance Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce parasitic capacitance in back-end-of-line interconnect structures while maintaining etch stop layers with moisture blocking properties, as scaling down device dimensions increases the role of BEOL structures in switching speed and power consumption, and current etch stop layers with greater etch resistance often lead to higher dielectric constants.
Innovation Solution
A method is introduced to form an etch stop layer structure comprising a low-density, low-dielectric-constant dielectric layer glued to a high-density dielectric layer using a glue layer, where the low-density layer reduces parasitic capacitance and the high-density layer acts as a hermetic moisture barrier, with the glue layer improving adhesion between the two layers, and the etch stop layer is formed using oxygen-free materials to avoid oxidation concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If etch stop layers with greater etch resistance are used, then etch resistance is improved, but dielectric constant increases leading to higher parasitic capacitance
Solution Approach 1:
The patent divides the etch stop layer into multiple distinct layers: a first etch stop layer with higher etch resistance and a second etch stop layer with lower etch resistance but lower dielectric constant. This segmentation allows each layer to perform its specialized function, resolving the contradiction between etch resistance and parasitic capacitance.
Solution Approach 2:
Different regions of the etch stop structure are assigned different material properties. The first etch stop layer uses materials with high etch resistance (such as silicon nitride or silicon carbonitride), while the second etch stop layer uses materials with lower dielectric constant (such as silicon oxide or porous low-k materials). This local differentiation optimizes both etch resistance and capacitance reduction.
2Productivity
If device dimensions are scaled down, then production efficiency and cost are improved, but parasitic capacitance from interconnect structures increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the etch stop layers by introducing a second etch stop layer with lower dielectric constant than the first etch stop layer. This parameter modification directly reduces parasitic capacitance in the interconnect structure, addressing the dynamic power loss issue that arises from device scaling.
3Loss of energy
If low-density, low-dielectric-constant dielectric layer is used, then parasitic capacitance is reduced, but moisture blocking capability deteriorates
Solution Approach 1:
The patent segments the moisture blocking function across two layers: the first etch stop layer provides primary moisture blocking with its high-density, oxygen-free material structure, while the second etch stop layer provides capacitance reduction. Together, they maintain overall moisture blocking capability while reducing parasitic capacitance.
Solution Approach 2:
The etch stop structure uses composite material architecture where the first etch stop layer (high-density material like silicon nitride) and second etch stop layer (low-k material like silicon oxide or porous dielectric) are combined. This composite structure leverages the strengths of each material type to achieve both moisture blocking and capacitance reduction.
Data Source
AI summary
A method according to the present disclosure includes receiving a workpiece that includes a first conductive feature embedded in a first dielectric layer, selectively depositing a capping layer over the first conductive feature, depositing a first etch stop layer (ESL) over the capping layer, depositing a glue layer over the first ESL, depositing a second ESL over the glue layer, depositing a second dielectric layer over the second ESL, forming an opening through the second dielectric layer, the second ESL, the glue layer, and the first ESL to expose the capping layer, and forming a second conductive feature in the opening. A density of the second ESL is greater than a density of the first ESL.