Dual-Depth Source-Drain Junctions for Mobility Without Leakage
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Solution Overview
Problem
Existing image sensor transistors face challenges in achieving optimal charge carrier mobility while minimizing current leakage, particularly due to deeper source and drain junctions which can lead to undesirable current leakage between adjacent transistors.
Innovation Solution
The implementation of dual-depth source and drain junctions, where shallow doped regions are formed at a uniform first depth and deep doped regions extend further into the semiconductor substrate, promotes complete charge carrier channel formation and prevents current leakage between adjacent transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If deeper source and drain junctions are formed to improve charge carrier mobility, then charge carrier mobility is improved, but current leakage between adjacent transistors increases
Solution Approach 1:
The source and drain junctions are segmented into two distinct depth regions: shallow doped regions and deep doped regions. This segmentation allows the shallow regions to provide good charge carrier mobility while the deep regions extend laterally to prevent current leakage between adjacent transistors, thus resolving the contradiction between mobility and leakage prevention.
Solution Approach 2:
Different regions of the source and drain junctions are given different doping depths to serve different functions. The shallow doped regions are optimized for charge carrier injection and mobility, while the deep doped regions are optimized for lateral confinement and leakage prevention. This local differentiation of quality allows simultaneous optimization of both mobility and leakage control.
2Area of moving object
If deeper junctions are formed to increase effective channel width, then effective channel width is increased, but current leakage between adjacent transistors increases
Solution Approach 1:
The junction structure is segmented vertically into shallow and deep doped regions. The deep doped regions provide lateral extension that increases the effective channel width, while the shallow doped regions maintain proper vertical alignment to prevent current leakage. This segmentation enables independent optimization of channel width and leakage prevention.
Solution Approach 2:
The solution transitions from a single-depth (one-dimensional) junction to a dual-depth (two-dimensional) junction structure. By adding the vertical depth dimension as a differentiating factor, the patent enables the deep doped regions to extend laterally for increased channel width while the shallow regions maintain vertical confinement to prevent leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances charge carrier movement around the full depth of the vertical gate portions, increasing the effective channel width and improving transistor performance, while effectively inhibiting current leakage between adjacent transistors.
Implementation Method 1
a first doped region and a second doped region are formed in the semiconductor substrate by doping
Data Source
AI summary
Transistors, electronic devices, and methods are provided. Transistors include a gate trench formed in a semiconductor substrate and extending to a gate trench depth, and a source and a drain formed as doped regions in the semiconductor substrate and having a first conductive type. The source and the drain are formed along a channel length direction of the transistor at a first end and a second end of the gate trench, respectively, and the source and the drain each includes a first doped region and a second doped region extending away from the first doped region. The second doped region extends to a depth in the semiconductor substrate deeper than the first doped region relative to a surface of the semiconductor substrate.