Dual Depth Shallow Trench Isolation for FinFET CMOS

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Solution Overview

Problem

Fabricating dual shallow trench isolation structures with varying depths in semiconductor processes is complex and difficult to integrate into existing CMOS processes, particularly for fin-type field effect transistor devices where different isolation depths are required for fins and well regions.

Innovation Solution

A method involving the formation of hard mask patterns, subsequent trench creation with different depths and widths, and the use of insulating layers formed through high-density-plasma CVD and flowable CVD or spin-coating processes, along with planarization steps using chemical mechanical polishing, to create dual isolation structures with distinct depths for fin and well regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual isolation structures with different depths are fabricated, then isolation performance for fins and well regions is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveisolation performanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure is segmented into two distinct depth levels: a first isolation structure for fin regions and a second isolation structure for well regions. This segmentation allows each isolation structure to be optimized independently for its specific functional requirements, improving overall isolation performance while maintaining manageable manufacturing complexity through modular fabrication steps.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different isolation depths are implemented locally according to specific regional requirements: deeper isolation for well regions and shallower isolation for fin regions. This local quality approach ensures that each region receives the appropriate isolation depth for its specific electrical and mechanical requirements, enhancing device reliability without requiring uniform complex structures throughout the entire substrate.

Inventive Principle:
Principle #3Local quality

2Reliability

If dual isolation structures with different depths are fabricated, then device performance is improved, but process complexity increases

Engineering Contradiction:
Improvedevice performanceVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A filling layer is formed in advance before the final isolation structures are created. This preliminary action establishes a reference plane and structural foundation that simplifies subsequent processing steps, allowing the first and second isolation structures to be formed with different depths more easily while maintaining overall process control and reducing the complexity of coordinating multiple deep etching and filling operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The filling layer acts as an intermediary element between the substrate and the final isolation structures. It provides a intermediate structural layer that facilitates the formation of dual-depth isolation structures by serving as a stopping point for etching processes and a foundation for selective removal, thereby simplifying the overall fabrication process while enabling differentiated isolation depths for optimal device performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method simplifies the integration of dual isolation structures with different depths into the existing CMOS process, enhancing device performance by providing better fin width control and isolation, thus overcoming the complexity of fabricating varied depth isolation structures.

Implementation Method 1

the first insulating layer is formed by a high-density-plasma CVD process

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 2

the second insulating layer is formed by a flowable CVD process or a spin-coating process

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

the second insulating layer is formed by a flowable CVD process or a spin-coating process

Methodology Applied
Scientific EffectSpin Coating: Spin Coating

Implementation Method 4

performing a first planarization step to the first insulating layer and the filling layer until tops of the hard mask patterns are exposed

Methodology Applied
Scientific EffectChemical Mechanical Polishing:

Data Source

PatentUS9105685B2Method of forming shallow trench isolation structure
Publication Date: 2015.08.11 UNITED MICROELECTRONICS CORP
  • US9105685B2 patent drawing
  • US9105685B2 patent drawing
  • US9105685B2 patent drawing

AI summary

A method of forming a shallow trench isolation structure is disclosed. Hard mask patterns are formed on a substrate. A portion of the substrate is removed, using the hard mask patterns as a mask, to form first trenches in the substrate, wherein a fin is disposed between the neighboring first trenches. A filling layer is formed in the first trenches. A patterned mask layer is formed on the filling layer. A portion of the filling layer and a portion of the fins are removed, using the patterned mask layer as a mask, to form second trenches in the substrate. A first insulating layer is formed on the substrate filling in the second trenches.