Dual Depth Shallow Trench Isolation for CMOS Image Sensor Leakage

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Solution Overview

Problem

Conventional single shallow trench isolation (STI) structures in CMOS image sensors fail to provide adequate isolation for both pixel array and periphery regions, leading to excessive dark current leakage and image degradation as pixel sizes scale down.

Innovation Solution

Implementing dual shallow trench isolation structures with different depths for the pixel array and periphery regions, where the pixel array region has a shallow STI depth (D1) and the periphery region has a deeper STI depth (D2), effectively isolating NMOS devices in the pixel array and both NMOS and PMOS devices in the periphery, reducing leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single STI structure is used for both pixel array and periphery regions, then device complexity is reduced, but dark current leakage increases

Engineering Contradiction:

Improveisolation structure complexityVSAvoiddark current leakage

Core Design Contradiction:

Device complexityVSObject-generated harmful factors

Solution Approach 1:

The isolation structure is segmented into two distinct STI structures: a first STI for the pixel array region and a second STI for the periphery region. This segmentation allows each STI to be optimized independently for its specific region, with the second STI providing deeper isolation to prevent dark current leakage while the first STI maintains appropriate isolation for pixel devices.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different isolation depths are applied to different regions: the pixel array region receives a first STI with a specific depth, while the periphery region receives a second STI with a greater depth. This local quality differentiation addresses the specific isolation requirements of each region, preventing dark current leakage in the periphery where it is most problematic.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If pixel size is scaled down, then sensor resolution is improved, but dark current leakage tolerance decreases

Engineering Contradiction:

Improvepixel sizeVSAvoiddark current leakage tolerance

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

As pixels scale down, the dual STI structure provides enhanced local isolation quality. The second STI in the periphery region extends deeper to compensate for the reduced tolerance to dark current leakage that accompanies smaller pixel dimensions, maintaining reliability despite increased manufacturing precision requirements.

Inventive Principle:

Principle #3Local quality

3Object-generated harmful factors

If STI depth is increased, then dark current leakage is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improvedark current leakageVSAvoidisolation structure depth variation

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The isolation structure is divided into two STI structures with different depths, allowing the deeper second STI to be implemented only where needed in the periphery region. This segmentation avoids the need to increase the depth of the entire isolation structure, thereby reducing manufacturing complexity while still achieving the goal of reducing dark current leakage.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11152414B2Image sensor including dual isolation and method of making the same

Publication Date: 2021.10.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An image sensor includes a substrate having a pixel region and a periphery region. The image sensor further includes a first isolation structure formed in the pixel region; the first isolation structure including a first trench having a first depth. The image sensor further includes a second isolation structure formed in the periphery region; the second isolation structure including a second trench having a second depth greater than the first depth. The pixel region includes only NMOS devices and the periphery region includes both NMOS and PMOS devices.