Array Substrate Etching Barrier for Dual-Depth Via Formation
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Solution Overview
Problem
The high manufacturing cost of conventional display panels is attributed to the need for a halftone mask to form via holes of different depths for the source-drain electrode and metal light-shielding layers simultaneously.
Innovation Solution
An array substrate design that includes a metal light-shielding layer, a buffer layer, an active layer, and an interlayer insulating layer with first and second via holes, where the active layer has an etching barrier layer with zirconium-doped metal oxide semiconductor materials, allowing for the formation of both types of via holes using an ordinary fully transparent mask, reducing etching impact on the active layer and enabling simultaneous formation of both types of holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a halftone mask is used to form via holes of different depths simultaneously, then the manufacturing precision of via holes is improved, but the manufacturing cost increases
Solution Approach 1:
The patent segments the active layer into two functional parts: a metal oxide body layer and an etching barrier layer. The etching barrier layer contains zirconium-doped metal oxide semiconductor materials that provide differential etching resistance, allowing the etching process to stop at different depths in different regions without requiring a halftone mask.
Solution Approach 2:
The etching barrier layer introduces local quality variation through zirconium doping, creating regions with different etching rates. This allows the same etching process to naturally create via holes of different depths in different areas, eliminating the need for expensive halftone masks while maintaining precise via hole formation.
2Productivity
If via holes of different depths are formed at the same time, then the productivity is improved, but the device complexity increases due to the halftone mask requirement
Solution Approach 1:
The etching barrier layer with zirconium-doped metal oxide semiconductor materials is formed in advance during the active layer fabrication process. This preliminary action embeds the depth-control functionality directly into the layer structure, enabling subsequent single-step etching to produce different via hole depths without complex masks.
Solution Approach 2:
The etching barrier layer acts as an intermediary between the etching process and the active layer. It mediates the etching process by providing differential etching resistance through zirconium doping, allowing a single etching step to create multiple via hole depths without requiring complex halftone mask intermediaries.
3Ease of manufacture
If an ordinary fully transparent mask is used instead of a halftone mask, then the manufacturing cost is reduced, but the etching effect on the active layer increases
Solution Approach 1:
The patent converts the potentially harmful over-etching effect into a beneficial feature by designing the etching barrier layer with zirconium-doped metal oxide semiconductor materials. The differential etching resistance of this layer allows the etching process to naturally terminate at appropriate depths in different regions, protecting the active layer while maintaining cost-effectiveness.
Solution Approach 2:
The etching barrier layer modifies the etching parameters locally through zirconium doping, changing the etching rate and selectivity in different regions. This parameter change enables the use of ordinary masks while preventing excessive etching damage to the active layer by creating natural etching stop points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the etching effect on the active layer, ensures electrical stability, saves process steps, and lowers photomask costs by using an ordinary mask to form both types of via holes at once, thereby reducing manufacturing costs.
Implementation Method 1
the etching barrier layer includes a plurality of metal oxide semiconductor materials doped with a zirconium element
Data Source
AI summary
An array substrate, a manufacturing method of the array substrate, and a display panel are provided. The array substrate includes a metal light-shielding layer, a buffer layer an active layer, an interlayer insulating layer, and a source-drain electrode layer, a plurality of first via holes are disposed in the interlayer insulating layer, the active layer includes a metal oxide body layer and an etching barrier layer disposed on a surface of the metal oxide body layer, the etching barrier layer includes a plurality of first etching barrier sections corresponding to the first via holes, and the source-drain electrode layer is electrically connected to the metal oxide body layer through the first etching barrier sections.