Dual-Destination Type Conversion for Mixed Precision Accumulation
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Solution Overview
Problem
Modern processors face inefficiencies in performing mixed-precision operations due to the need for type conversions and increased register requirements, particularly when converting between single-precision and double-precision data, which can lead to errors in accumulation and memory operations.
Innovation Solution
The introduction of instructions that support dual-destination type conversion, mixed-precision accumulation, and atomic memory operations, allowing for the conversion of single-precision data to double-precision data within a single instruction, reducing the instruction count and improving symmetry across multiple vector ports, in compliance with IEEE 754 standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If double precision floating point computations are used to increase accuracy, then measurement precision is improved, but device complexity increases and productivity decreases
Solution Approach 1:
The processor divides the 512-bit vector register into multiple lanes, with each lane handling a portion of the data elements. This segmentation allows different precision operations to be performed on different segments simultaneously, enabling mixed-precision computations where some lanes use double precision for accuracy-critical calculations while other lanes use single precision for throughput-critical calculations.
Solution Approach 2:
The patent implements local quality by allowing different precision modes within the same vector operation. Specific data elements or lanes can be designated for double precision computation when higher accuracy is required, while other elements use single precision. This localized precision assignment optimizes both accuracy and performance by applying high precision only where necessary.
2Measurement precision
If double precision floating point computations are used to increase accuracy, then measurement precision is improved, but the number of instructions increases
Solution Approach 1:
The patent merges type conversion and accumulation operations into a single unified instruction. The VCVTUPS2PD instruction simultaneously performs type conversion from unsigned integer to double precision floating point and accumulation into a vector register, eliminating the need for separate conversion and addition instructions. This merging reduces instruction count and improves execution efficiency while maintaining double precision accuracy.
3Measurement precision
If type conversion instructions are used to convert single precision to double precision, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines type conversion and accumulation functions into a single instruction VCVTUPS2PD. This merged instruction performs the complete operation sequence of converting unsigned integer data to double precision floating point format and then accumulating the result into a destination vector register, thereby reducing the total number of instructions required and simplifying the execution pipeline.
Solution Approach 2:
The instruction design incorporates multi-functionality by enabling a single instruction to perform multiple operations: type conversion from unsigned integer to double precision, data accumulation, and vector register management. This universal instruction handles what would traditionally require multiple specialized instructions, reducing overall system complexity.
Data Source
AI summary
Disclosed embodiments relate to instructions for dual-destination type conversion, accumulation, and atomic memory operations. In one example, a system includes a memory, a processor including: a fetch circuit to fetch the instruction from a code storage, the instruction including an opcode, a first destination identifier, and a source identifier to specify a source vector register, the source vector register including a plurality of single precision floating point data elements, a decode circuit to decode the fetched instruction, and an execution circuit to execute the decoded instruction to: convert the elements of the source vector register into double precision floating point values, store a first half of the double precision floating point values to a first location identified by the first destination identifier, and store a second half of the double precision floating point values to a second location.