Dual-Detector PLL Switching for Faster Lock and Lower Power
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Solution Overview
Problem
Existing phase lock loops (PLLs) in integrated circuits face challenges in rapidly locking frequency and phase, leading to increased time and power consumption when switching between low-frequency idle and high-frequency performance states.
Innovation Solution
The PLL comprises a first and second detector, a multiplexer, a filter, an oscillator, and a feedback circuit, which allows for rapid frequency and phase locking by alternating signal processing modes based on a ready signal, enabling fast transitions between operational states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional phase lock loop is used for frequency and phase locking, then the system can maintain stable clock synchronization, but the time and power consumption increase when switching between low-frequency idle and high-frequency performance states
Solution Approach 1:
The patent implements dynamic switching between two operational modes (first mode with first detector for frequency locking, second mode with second detector for phase locking) based on the ready signal state. This dynamic adaptation allows the PLL to optimize performance by using aggressive frequency acquisition initially, then transitioning to precise phase tracking, thereby reducing overall locking time and power consumption during state transitions.
Solution Approach 2:
The phase lock loop is segmented into two distinct operational phases: frequency locking phase (using first detector and first filter) and phase locking phase (using second detector and second filter). This segmentation allows each detector-filter combination to be optimized for its specific function, enabling faster convergence and reduced power consumption by activating only the necessary components for the current operational phase.
2Loss of time
If a phase lock loop rapidly locks frequency and phase, then the switching time between operational states is reduced, but the circuit complexity increases
Solution Approach 1:
The patent employs dynamic mode switching controlled by the ready signal to achieve rapid locking. The system transitions from a first operational mode (frequency detection and correction) to a second operational mode (phase detection and correction) based on whether the ready signal is high or low. This dynamic adaptation enables fast frequency acquisition followed by quick phase settling, significantly reducing total locking time while managing circuit complexity through controlled activation of different detector-filter paths.
3Productivity
If the PLL uses a single detector and filter for both frequency and phase locking, then the device complexity is reduced, but the locking performance and speed are compromised
Solution Approach 1:
The patent divides the locking function into two segregated paths: a first path with a first detector and first filter dedicated to frequency locking, and a second path with a second detector and second filter dedicated to phase locking. This functional segmentation allows each detector-filter pair to be optimized for its specific task, achieving superior locking performance and faster convergence speeds compared to a unified detector-filter approach.
Solution Approach 2:
The patent implements a multi-functional detector system where the first detector is specifically optimized for frequency detection and the second detector for phase detection. Each detector type provides specialized functionality that enhances overall locking performance, with the system intelligently selecting which detector to use based on the current operational phase indicated by the ready signal.
Data Source
AI summary
Phase lock loop with improved performances and related method; the former may comprise a first detector, a second detector, a multiplexer, a filter, an oscillator, a frequency-divider and a feedback circuit. The first detector may be coupled to a reference node, a frequency-division node, a first node and a lock-control node. The second detector may be coupled to the reference node, a feedback node and a second node. The multiplexer may be coupled to the first node, the second node, the lock-control node and a filter node. The filter may be coupled to the filter node and a third node. The oscillator may be coupled to the third node and a fourth node. The frequency-divider may be coupled to the fourth node and the frequency-division node. The feedback circuit may be coupled to the reference node, the fourth node, the lock-control node and the feedback node.