Dual Dice Latch Circuit for Soft-Error-Resistant Data Storage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional dice latches have complex circuit designs that consume significant area on a semiconductor die and are difficult to fabricate, often requiring numerous transistors and being susceptible to soft errors from radiation.

Innovation Solution

A simplified dice latch design using a combined dual latch circuit with fewer transistors (12 or 14) that includes cross-coupled latches and data node switches, providing robustness against soft errors through pull-up and pull-down circuits, and optional reset circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional dice latch designs are used, then data storage reliability is improved, but circuit complexity increases and area consumption grows

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines two latches into a single integrated dice latch structure where the latches share common circuit elements and are tightly coupled. This merging approach maintains the dual-interlocked functionality for reliable data storage while reducing the total transistor count and circuit complexity compared to using two separate latches.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If conventional dice latch designs with many transistors are used, then data storage reliability is improved, but area consumption increases

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidarea consumption
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By merging two latches into a single dice latch structure with shared circuit elements, the patent achieves reliable data storage while significantly reducing the area consumption on the semiconductor die compared to conventional designs that use more transistors and separate latch structures.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If conventional dice latch designs are used, then data storage reliability is improved, but ease of manufacture deteriorates

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidease of fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The merged dice latch structure with its integrated design and shared circuit elements simplifies the fabrication process by reducing the number of separate components that need to be manufactured and assembled, while maintaining the dual-interlocked functionality for reliable data storage.

Inventive Principle:
Principle #5Merging (Combining)

4Reliability

If conventional dice latch designs are used, then data storage reliability is improved, but the number of fabrication steps increases

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidnumber of fabrication steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The integrated dice latch design combines multiple functions into a single structure that can be fabricated in fewer steps compared to conventional designs. The merged architecture allows for simultaneous formation of multiple circuit elements during the fabrication process, reducing the total number of fabrication steps required.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12394456B2Apparatuses and methods including dice latches in a semiconductor device
Publication Date: 2025.08.19 MICRON TECHNOLOGY INC
  • US12394456B2 patent drawing
  • US12394456B2 patent drawing
  • US12394456B2 patent drawing

AI summary

According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.