Dual Die Semiconductor Package Address Timing Alignment

The patent divides the address timing control into separate segments for each die. Each die has its own address buffer (first address buffer for first die, second address buffer for second die) that can be independently controlled. This segmentation allows each die to have independent delay control, enabling precise timing alignment despite different PVT conditions, while still sharing the same address pins.

The patent changes the delay parameter of each address buffer independently based on PVT conditions. The controller adjusts the delay time of the first address buffer and second address buffer separately to compensate for process, voltage, and temperature variations in each die. This parameter adjustment ensures that address timing is aligned across dies with different characteristics.

The patent performs preliminary delay adjustment of address buffers before the actual address training operation. By pre-adjusting the delay parameters of first and second address buffers based on initial PVT characterization, the system reduces the range of timing variations that need to be compensated during training. This preliminary action shortens the subsequent training time while maintaining operational stability.

The patent implements a feedback mechanism where the controller monitors address timing alignment between dies during training and adjusts delay parameters accordingly. The controller receives timing information from both dies and modifies the delay of address buffers to achieve optimal alignment, creating a closed-loop system that efficiently converges to the correct timing parameters.