Dual Die Package Electrode Pad Positioning for Signal Delay Consistency
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Solution Overview
Problem
Existing Dual Die Package (DDP) semiconductor packages face challenges in maintaining consistent wire length between stacked semiconductor chips, leading to variations in signal delay time, which hinders high-speed operations.
Innovation Solution
The semiconductor device configuration ensures equal wire length by positioning electrode pad rows and external electrodes on the same end portions of the substrate, with specific arrangements of I/O and CA pads connected to corresponding external electrodes, reducing wire length variations and signal delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrode pad rows and external electrodes are arranged in conventional positions on semiconductor chips and substrate, then standard packaging design is achieved, but wire length varies between chips causing signal delay time variations
Solution Approach 1:
The patent applies asymmetry by positioning electrode pad rows and external electrodes at corresponding end portions of the substrate rather than using symmetric or conventional arrangements. Specifically, the first electrode pad row is positioned at a first end portion of the first semiconductor chip and connected to first external electrodes at a first end portion of the substrate, while the second electrode pad row is positioned at a second end portion and connected to second external electrodes at the second end portion. This asymmetric positioning ensures equal wire lengths from each electrode pad row to its corresponding external electrodes, eliminating signal delay variations between chips.
2Speed
If wire length between semiconductor chip and external electrodes is not controlled, then manufacturing is simpler, but input/output capacitance varies and signal delay time increases
Solution Approach 1:
The patent implements preliminary action by pre-positioning the electrode pad rows at specific end portions of the semiconductor chips and the external electrodes at corresponding end portions of the substrate during the design and manufacturing process. This preliminary positioning ensures that the wire lengths from each electrode pad row to its corresponding external electrodes are equal before the chips are mounted and wired. By establishing this configuration in advance, the patent eliminates the need for post-manufacturing wire length adjustments and ensures consistent signal transmission speed across all chips.
3Ease of manufacture
If electrode pads are connected to external electrodes with varying wire lengths, then wiring flexibility is improved, but input/output capacitance increases and timing variations occur
Solution Approach 1:
The patent applies equipotentiality by ensuring that all wire connections from electrode pad rows to external electrodes have equal lengths, thereby creating equal electrical paths. The first wire connecting the first electrode pad row to the first external electrodes has the same length as the second wire connecting the second electrode pad row to the second external electrodes. This equipotential approach ensures that signal delay times are identical for all connections, eliminating timing variations while maintaining wiring flexibility through the end-portion positioning strategy.
Data Source
AI summary
A semiconductor device comprises a substrate, pluralities of first and second external electrodes formed in two end portions of one surface of the substrate, a first semiconductor chip mounted on the other surface of the substrate, the first semiconductor chip having an electrode pad row formed in one end portion of one surface of the first semiconductor chip and electrically connected to the first external electrodes, the first semiconductor chip being disposed so that the one end portion of the first semiconductor chip is positioned on an end portion on which the first external electrodes of the substrate are formed, and a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip having an electrode pad row formed in one end portion of one surface of the second semiconductor chip and electrically connected to the second external electrode, the second semiconductor chip being disposed so that the one end portion of the second semiconductor chip is positioned on an end portion on which the second external electrodes of the substrate are formed.