Dual Directory Coherency Mapping for Heterogeneous Scale-Out Systems
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Solution Overview
Problem
Maintaining coherency in heterogeneous systems is challenging, particularly in scale-out systems where diverse processing elements like GPU, FPGA, and ARM architectures need to share and access data efficiently with low latency and energy efficiency.
Innovation Solution
A dual directory based coherency mapping method is employed, utilizing a high-speed interface like RapidIO for scalable computer systems, enabling coherent communication between heterogeneous processing elements by implementing a two-level directory/snoop filter protocol, which can be used in conjunction with existing non-coherent protocols to support energy-efficient scale-out systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual directory based coherency mapping method is used, then data coherence is maintained across heterogeneous processing elements, but system complexity increases
Solution Approach 1:
The coherency system is segmented into two separate directories: a first directory implemented within the on-chip fabric for tracking cache coherent data among on-chip cores, and a second directory implemented in the scale-out module for tracking participating processing elements. This segmentation allows each directory to handle specific coherency responsibilities independently, maintaining data coherence while distributing system complexity across modular components.
Solution Approach 2:
The scale-out module acts as an intermediary between the on-chip coherent fabric and external processing elements. It implements the second directory and handles coherency tracking for external PEs, mediating coherency maintenance between the internal on-chip system and external heterogeneous processing elements, thereby maintaining overall system coherence without requiring direct complex interactions between all components.
2Speed
If high-speed interface like RapidIO is used for scale-out, then communication latency is reduced, but energy consumption increases
Solution Approach 1:
The system dynamically selects between coherent and non-coherent protocols based on the specific data access requirements and processing element interactions. The scale-out module can operate in coherent mode using RapidIO for latency-critical communications, while falling back to non-coherent protocols for less time-sensitive operations, thereby optimizing the balance between communication speed and energy consumption.
Solution Approach 2:
The coherency protocol parameters are configurable and adaptable based on system workload and performance requirements. The system can adjust the level of coherency enforcement, directory update frequency, and protocol selection to change operational parameters, allowing optimization of energy consumption while maintaining acceptable communication latency for different application scenarios.
3Productivity
If coherent communication protocol is implemented across heterogeneous architectures, then data sharing efficiency is improved, but adaptability to different architectures becomes more difficult
Solution Approach 1:
The scale-out module implements a universal coherency interface that can work with multiple heterogeneous processing element architectures including GPUs, FPGAs, and ARM processors. The dual directory structure provides a unified mechanism for tracking cache coherent data across diverse architectures, enabling efficient data sharing while maintaining compatibility with different processor types through standardized coherency protocols.
Solution Approach 2:
Each processing element interface is customized with architecture-specific adaptations while maintaining the overall universal coherency framework. The system applies local quality adjustments at each PE interface to handle architecture-specific requirements, allowing the universal coherency protocol to adapt to different processor architectures without sacrificing data sharing efficiency or requiring complete protocol redesign for each architecture.
Data Source
AI summary
Scalable Coherent Apparatus and Method have been disclosed. In one implementation a dual directory approach is used to implement scalable coherent accesses in a heterogeneous system. A transaction identification mapping for coherent RapidIO memory transactions between a plurality of external hardware processing elements is used. Source transaction identification encoding is a combination of bits from two advanced extensible interface identifications. Target transaction identification is decoded into a combination of bits for two advanced extensible interface identifications.