Dual DLL Clock Selection for Faster Memory Data Synchronization
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Solution Overview
Problem
Current semiconductor memory apparatuses face challenges in achieving high data access speed due to delays in the system clock signal as it passes through clock input buffers and transmission lines, leading to synchronization issues and increased power consumption, and are prone to a 'stuck phenomenon' during delay locked states.
Innovation Solution
The semiconductor memory apparatus employs two delay locked loops and a clock selection block to generate a delay locked clock by delaying the system clock and its inverse signal, allowing for independent phase comparisons and control of delay amounts, which reduces locking time and prevents the stuck phenomenon by selecting the faster locked clock as the reference for data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single delay locked loop is used to compensate for clock path delay, then the system can achieve synchronization, but the locking time becomes excessively long and the system is prone to stuck phenomenon
Solution Approach 1:
The patent divides a single delay locked loop into two separate delay locked loops operating in parallel. Each DLL handles half of the clock cycle (one for rising edge, one for falling edge), allowing independent locking processes that reduce overall locking time and prevent stuck phenomenon by providing redundancy
Solution Approach 2:
The patent generates both delay locked clocks in advance during the locking period, allowing the system to quickly switch to synchronized operation. The phase comparators and delay lines are prepared and adjusted simultaneously, reducing the overall locking time to approximately half of a single DLL approach
2Reliability
If the system clock is delayed to compensate for path delay, then data can be synchronized with the system clock, but the data access speed decreases
Solution Approach 1:
The patent dynamically adjusts the delay amount in each delay locked loop based on phase comparison results. The delay lines are configured with multiple tap points that allow fine-grained adjustment of delay values, enabling the system to achieve minimum necessary delay for synchronization while maximizing data access speed
Solution Approach 2:
The patent changes the delay parameter of the clock signal by exactly the amount needed to compensate for the clock path delay. The phase comparators continuously monitor and adjust the delay amount, ensuring optimal synchronization without excessive delay that would reduce data access speed
3Reliability
If the delay locked loop delays the system clock by a large amount, then synchronization is achieved, but the locking range becomes limited and stuck phenomenon occurs
Solution Approach 1:
The patent segments the total delay requirement into two separate delay locked loops, each handling a portion of the delay. This division allows each DLL to operate within an optimal locking range while collectively achieving the total required delay compensation, thereby expanding the overall locking range and preventing stuck phenomenon
Solution Approach 2:
The patent performs preliminary delay adjustment in both DLLs simultaneously during the locking period. The phase comparators pre-adjust the delay lines to appropriate values before full synchronization is required, ensuring that the system operates within the optimal locking range and avoids stuck phenomenon
Data Source
AI summary
A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.